4 ms·
Naively as a West Coast Verilog person, VHDL Delta cycles seem like a nice idea, but not what actual circuits are doing by default. The beauty and the terror of
by buildbot 6mo ago
Naively as a West Coast Verilog person, VHDL Delta cycles seem like a nice idea, but not what actual circuits are doing by default. The beauty and the terror of Verilog is the complete, unconstrained parallel nature of it’s default - it all evaluates at t=0 by default, until you add clocks and state via registers. VHDL seems easy to create latches and other abominations too easily. (I am probably wrong at least partially.)
((Shai-Hulud Desires the Verilog))
- tverbeure 6mo agoAFAIK, creating latches is just as easy in Verilog as in VHDL. They use the same model to determine when to create one. But with a solid design flow (which should include linting tools like Spyglass for both VHDL and Verilog), it’s not a major concern.
- nickelpro 6mo agoSystemVerilog basically fixes this with always_comb vs always_latch. There's no major implementation which doesn't handle warning or even failing the flow on accidental latch logic inside an always_comb.
- hrmtst93837 6mo ago[flagged]
- buildbot 6mo agoThat does sound like my experience…
- tverbeure 6mo ago> Once the design gets past toy size, Do you consider 800+mm2 slabs of 3nm of silicon still toy size? Because there's a very high chance that those were written in Verilog, and I've never had to chase sim vs synthesis mismatches. > Verilog gives you enough rope. Yes. If you don't know what you're doing and don't follow the industry standard practises.
- oelang 6mo ago(System)Verilog has delta cycles too you know, they call it an event queue, but it's basically the same. It's the direct variable updates that happen outside of this mechanism that cause all the issues. Imho it was a poor attempt at simulation optimization, and now you can't take it out of the language anymore.
- buildbot 6mo agoI did not know!