3 ms·
Most of the time. But sometimes, no. See ATL thunk emulation (last I checked, still alive in the windows kernel) and ntvdm handling of the BOP pseudoinstruction
by lolsowrong 6mo ago
Most of the time. But sometimes, no. See ATL thunk emulation (last I checked, still alive in the windows kernel) and ntvdm handling of the BOP pseudoinstruction.
See also: Jazelle DBX.
Hell, on modern x86 processors, many “native” instructions are actually a series of micro-ops for a mostly undocumented and mostly poorly understood microcode architecture that differs from the natively documented instruction set.
It’s turtles all the way down.
- saagarjha 6mo agoJazelle and micro-ops are not interpreters, they are executed in hardware.
- lolsowrong 6mo agoI believe only some parts of Jazelle are handled in hardware, though I don’t know if anybody has got their hands on any of the bits of the software side. I do know there’s documentation on handling unimplemented instructions. I don’t know how I feel about micro-ops being executed in hardware - I mostly agree, but also, microcode updates exist…
- fc417fc802 6mo agoAn interpreter implemented in hardware is still an interpreter. Hot take, all machine instruction sets are scripting languages and LLVM is a transpiler.
- fc417fc802 6mo agoAren't all of them microcoded? Some years back root was achieved on a line of intel processors and new instructions implemented as proof of concept. There's an academic paper, citation not immediately to hand.
- lolsowrong 6mo agoI saw the paper from Google last year and thought something in it aligned with not everything running through the microcode engine, though I could be wrong.
- fc417fc802 6mo agoMight well be the case. I don't think I'm familiar with the paper you're referring to; any chance of at least a vague description?
- lolsowrong 6mo agoCan’t find the pdf, but it’s all related to the zentool stuff: https://github.com/google/security-research/blob/master/pocs/cpus/entrysign/zentool/docs/intro.md https://github.com/google/security-research/blob/master/pocs... Tavis spells it out there pretty quickly: “ The simplest instructions (add, sub, mov, etc) are all implemented in hardware. The more complicated instructions like rdrand, fpatan and cmpxchg are microcoded. You can think of them as a bit like calling into a library of functions written in that RISC-like code.”
- trynumber9 6mo agoSome instructions are microcoded but others take the fast path and avoid the microcode sequencer. Can't patch the latter in microcode RAM.