4 ms·
Really? Pretty much all atomics i’ve used have load, store of various integer sizes. I wrote a ring buffer in Go that’s very similar to the final design here us
by jitl 7mo ago
Really? Pretty much all atomics i’ve used have load,
store of various integer sizes. I wrote a ring buffer in Go that’s very similar to the final design here using similar atomics.
https://pkg.go.dev/sync/atomic#Int64 https://pkg.go.dev/sync/atomic#Int64
- dalvrosa 7mo agoNice one, thanks for sharing. Do you wanna share the ring buffer code itself?
- wat10000 7mo agoThey generally map directly to concepts in the CPU architecture. On many architectures, load/store instructions are already guaranteed to be atomic as long as the address is properly aligned, so atomic load/store is just a load/store. Non-relaxed ordering may emit a variant load/store instruction or a separate barrier instruction. Compare-exchange will usually emit a compare and swap, or load-linked/store-conditional sequence. Things like atomic add/subtract often map to single instructions, or might be implemented as a compare-exchange in a loop. The exact syntax and naming will of course differ, but any language that exposes low-level atomics at all is going to provide a pretty similar set of operations.
- dalvrosa 7mo ago100% agree +1
- jitl 7mo agoyeah that’s why i was surprised by grandparent saying the atomics were c++ specific
- pjdesno 7mo agoWhat's not guaranteed for "normal" loads and stores on many architectures is the order in which writes become visible to other CPU cores.
- wat10000 7mo agoRight, that's what the various memory ordering constants are for in C++ atomics, and other languages will likely have an equivalent. On such architectures, those will emit special instructions or barriers.