This project has moved to https://dauug.org https://dauug.org. Dauug|36 will be a 36-bit, 10 MIPS, open-source, maker-constructable minicomputer with preemptiv

This project has moved to https://dauug.org https://dauug.org. Dauug|36 will be a 36-bit, 10 MIPS, open-source, maker-constructable minicomputer with preemptive multitasking, paged virtual memory, and no "complex VLSI" (no microprocessor, FPGA, PLD, ASIC, or DRAM). The basic "logic gate" of Dauug|36 is a synchronous static RAM IC (SRAM), which is loaded with a fixed truth table (firmware) at startup, allowing each "gate" to compute any deterministic function of 18 input bits and up to 18 output bits. The CPU is implemented as 22 of these "gates" (read-only SRAMs containing firmware) and some trivial 74AUC glue logic. The instruction set is refreshingly robust and has ~190 opcodes so far.