I'm the author. The 5500FP is a complete 24-trit balanced ternary RISC processor implemented on an Efinix Trion T20F256 FPGA, with a custom open hardware deve

I'm the author. The 5500FP is a complete 24-trit balanced ternary RISC processor implemented on an Efinix Trion T20F256 FPGA, with a custom open hardware development board (GargantuRAM). The ISA is fully documented, including instruction formats, privilege model, and a trit-based data hierarchy. Full ISA docs and hardware at https://www.ternary-computing.com/docs/assembly/ISA/doc_index.html https://www.ternary-computing.com/docs/assembly/ISA/doc_inde... Mainboard OpenHardware: https://github.com/Ternary-Computer-System/GargantuRAM https://github.com/Ternary-Computer-System/GargantuRAM Very simple OS: https://github.com/MOS5500/GRam_OS https://github.com/MOS5500/GRam_OS Happy to answer questions on this architecture.