2 ms·
The large area usage was a surprise. But is the real PIO also this huge? My point is, maybe this is one of those designs that blow up in FPGA. Or maybe the ope
by throwa356262 7mo ago
The large area usage was a surprise. But is the real PIO also this huge?
My point is, maybe this is one of those designs that blow up in FPGA. Or maybe the open source version of the PIO is simply not as area efficient as the rpi version?
- phire 7mo agoBarrel shifters are one of those things that end up a lot bigger in FPGAs than ASICs. Not really because a barrel shifter is harder, but because FPGAs optimise for most other common building blocks and barrel shifters are kind of left behind. But even on the real RP2040, PIO is not small. Take a look at the annotated die shot [0]. The PIO blocks are notably bigger than the PROC blocks. [0] https://assets.raspberrypi.com/static/floorplan@2x-a25341f505669cd4b895d7b2b47d22c9.png https://assets.raspberrypi.com/static/floorplan@2x-a25341f50...
- bunnie 7mo agoIt's hard to know for sure, because we don't have access to the PIO's implementation, but I suspect that the PIO is "not small". That being said - size isn't everything. At these small geometries you have gates to burn, and having access to multiple shifts in a single cycle really do help in a range of serialization tasks.