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I think a bigger issue though is high clock speeds forced on the industry for marketing reasons. Current pipelines are way way to deep, but they can never come

I think a bigger issue though is high clock speeds forced on the industry for marketing reasons. Current pipelines are way way to deep, but they can never come down because that would decrease clock rates and lots of people have been trained into believing that clock speeds indicate performance. If Intel & AMD could convince the world to ignore clock rates, we'd get chips that had slightly higher throughput with much lower power consumption and slightly faster design cycles.

MichaelSalib 14y ago
Whoah. Downvoters, care to explain your logic here? Or do you think that 30+ stage pipeline in actually optimal for improving ILP?
- rz2k 14y ago
  I didn't downvote but: >they can never come down because that would decrease clock rates and lots of people have been trained into believing that clock speeds indicate performance is a bold statement that is not likely to be true. Casual metrics of performance change, and I doubt there are many people confused as to whether they choose a 4GHz Pentium 4 over a lower clocked Core 2, much less something like a Xeon E5.
  - wmf 14y ago
    Perhaps people are not confused simply because those older processors are no longer sold. AMD certainly felt the need to fudge their frequency back in the K7 days (although megahurtz marketing may be specific to the desktop market).
- wmf 14y ago
  I didn't downvote you, but there is research from Intel, IBM, and others showing that very deep pipelines (they disagree on the exact numbers) are indeed optimal if power isn't a concern (which it wasn't until ca. 2003). http://web.archive.org/web/20021211202017/http://systems.cs.colorado.edu/ISCA2002/ http://web.archive.org/web/20021211202017/http://systems.cs....
alanctgardner2 14y ago
I think you're being downvoted because your premise is flawed; we're at an OK place with respect to pipe depth versus clock speed. As early as the Athlon line people began to realize that clock doesn't directly map to speed, and recently Intel's move to the i3, i5, i7 models really pushed consumers away from a clock-based definition of speed. Anecdotally, I have an elderly neighbour who bought an i7 laptop, not because it was the higher number, but because her friend had told her that it was higher quality. Inadvertently, this tech-illiterate person had inferred that an i3 was somehow going to fail sooner or produce inferior results, because of the marketing Intel had performed. This kind of branding is far more powerful than Ghz nowadays, and it's a story that Intel more or less gets to make up. The only people technical enough to bother looking for a clock speed now probably understand all of the marketing jargon, more or less. To return to the original point; Intel's marketing isn't dictated by what people want, Intel's marketing dictates what people want. They aren't trying to make higher clocked chips to convince people they're better. They have a dominant market position.
- MichaelSalib 14y ago
  Every CPU designer I've spoken with thinks that pipelines are way too deep and clocks are way too fast, especially given memory bandwidth and latencies. So I don't see how we could be at an "OK place". Perhaps I've only spoken with ignorant CPU designers at Intel and AMD? Obviously, technically sophisticated people understand that clock speed is not the sole determinant of performance, but a lot of people making purchasing or marketing decisions aren't that sophisticated.
  - alanctgardner2 14y ago
    I don't mean to disparage your sources, but if everyone in engineering at the two biggest desktop CPU designers thinks pipelines are too deep in current designs, we should be seeing a big change. I understand bureaucracy well enough, but I think if everyone at AMD knew how to magically improve their current design, they would have done it by now. At this point, marketing wouldn't hold them back from assuming a dominant position technically, especially not in the server space. I've probably gotten in past my depth at this point, but it seems like the bigger complaint is memory latency and bandwidth. My understanding was that this was part of the move to on-die memory controllers and increasing levels of L2 and L3 cache.
Symmetry 14y ago
This was the case around the turn of the millenium, back when you had Pentium 4s that had over 30 stages in their pipelines. But those weren't really as good as AMD's less pipelined Athalon chips, and eventually Intel shifted from it's Pentium 4 lineage to the much more reasonable architecture derived from the Pentium 3, through the Pentium M, and then the Core architecture. These had around 15 pipeline stages, and despite their slower clocks the Core processors could out-preform the Pentium 4s. So the changes that you're saying could never happen did happen, and nearly a decade ago.

MichaelSalib 14y ago

Whoah. Downvoters, care to explain your logic here? Or do you think that 30+ stage pipeline in actually optimal for improving ILP?

rz2k 14y ago
I didn't downvote but: >they can never come down because that would decrease clock rates and lots of people have been trained into believing that clock speeds indicate performance is a bold statement that is not likely to be true. Casual metrics of performance change, and I doubt there are many people confused as to whether they choose a 4GHz Pentium 4 over a lower clocked Core 2, much less something like a Xeon E5.
- wmf 14y ago
  Perhaps people are not confused simply because those older processors are no longer sold. AMD certainly felt the need to fudge their frequency back in the K7 days (although megahurtz marketing may be specific to the desktop market).
wmf 14y ago
I didn't downvote you, but there is research from Intel, IBM, and others showing that very deep pipelines (they disagree on the exact numbers) are indeed optimal if power isn't a concern (which it wasn't until ca. 2003). http://web.archive.org/web/20021211202017/http://systems.cs.colorado.edu/ISCA2002/ http://web.archive.org/web/20021211202017/http://systems.cs....

alanctgardner2 14y ago

I think you're being downvoted because your premise is flawed; we're at an OK place with respect to pipe depth versus clock speed. As early as the Athlon line people began to realize that clock doesn't directly map to speed, and recently Intel's move to the i3, i5, i7 models really pushed consumers away from a clock-based definition of speed. Anecdotally, I have an elderly neighbour who bought an i7 laptop, not because it was the higher number, but because her friend had told her that it was higher quality. Inadvertently, this tech-illiterate person had inferred that an i3 was somehow going to fail sooner or produce inferior results, because of the marketing Intel had performed. This kind of branding is far more powerful than Ghz nowadays, and it's a story that Intel more or less gets to make up. The only people technical enough to bother looking for a clock speed now probably understand all of the marketing jargon, more or less. To return to the original point; Intel's marketing isn't dictated by what people want, Intel's marketing dictates what people want. They aren't trying to make higher clocked chips to convince people they're better. They have a dominant market position.

MichaelSalib 14y ago
Every CPU designer I've spoken with thinks that pipelines are way too deep and clocks are way too fast, especially given memory bandwidth and latencies. So I don't see how we could be at an "OK place". Perhaps I've only spoken with ignorant CPU designers at Intel and AMD? Obviously, technically sophisticated people understand that clock speed is not the sole determinant of performance, but a lot of people making purchasing or marketing decisions aren't that sophisticated.
- alanctgardner2 14y ago
  I don't mean to disparage your sources, but if everyone in engineering at the two biggest desktop CPU designers thinks pipelines are too deep in current designs, we should be seeing a big change. I understand bureaucracy well enough, but I think if everyone at AMD knew how to magically improve their current design, they would have done it by now. At this point, marketing wouldn't hold them back from assuming a dominant position technically, especially not in the server space. I've probably gotten in past my depth at this point, but it seems like the bigger complaint is memory latency and bandwidth. My understanding was that this was part of the move to on-die memory controllers and increasing levels of L2 and L3 cache.

Symmetry 14y ago

This was the case around the turn of the millenium, back when you had Pentium 4s that had over 30 stages in their pipelines. But those weren't really as good as AMD's less pipelined Athalon chips, and eventually Intel shifted from it's Pentium 4 lineage to the much more reasonable architecture derived from the Pentium 3, through the Pentium M, and then the Core architecture. These had around 15 pipeline stages, and despite their slower clocks the Core processors could out-preform the Pentium 4s. So the changes that you're saying could never happen did happen, and nearly a decade ago.