Interesting project. The observation that software-defined interfaces are becoming too slow for high-speed control loops is spot on. 86,443 cells for a clean L

Interesting project. The observation that software-defined interfaces are becoming too slow for high-speed control loops is spot on. 86,443 cells for a clean LVS/DRC design on Sky130 — that's solid for a 4-stage deep pipeline. Have you benchmarked power consumption? Curious how it compares to FPGA implementations of similar architectures.