5 ms·
It sounds like they didn't do a good job of putting the DIMM version in the hands of folks who'd write the drivers just for fun. The read path is sort of a was
by myself248 7mo ago
It sounds like they didn't do a good job of putting the DIMM version in the hands of folks who'd write the drivers just for fun.
The read path is sort of a wash, but writes are still unequalled. NAND writes feel like you're mailing a letter to the floating gate...
- zozbot234 7mo agoIsn't this addressed by newer PCIe standards? Of course, even the "new" Optane media reviewed in OP is stuck on PCIe 4.0...
- hedora 7mo agoNo; the issue with the DIMMs wasn’t drivers. The issue was that the only people allowed to target the DIMMs directly were the xeon hardware team. There was a startup doing good work with similar storage chips that were pin (BGA) compatible with standard memory. Not sure what happened to them. That’d be easier to program than xpoint. As for the new PCIe standard (you probably mean CXL), that’s also basically dead on arrival. The CPU is the power and money bottleneck for the applications it targets, so they provide a synchronous hardware API that stalls the processor pipeline when accessing high-latency devices. Contrast this to NVMe, which can be set up to either never block the CPU or amortize multiple I/Os per cache miss. Companies like NVIDIA are already able to maintain massive I/O concurrency over PCIe without CXL, because they have a programming model (the GPU) that supports it. CXL might be a small win for that.
- rando1234 7mo agoInteresting perspective re CXL synchronous API. Wouldn't things like OOO execution and speculation help with that? And anyway the latency is supposed to be comparable to NUMA latency, is that really such a deal breaker?