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> Also the bit manipulation extension wasn't part of the core. This is primarily because core is primarily a teaching ISA. One of the best parts about RiscV is

> Also the bit manipulation extension wasn't part of the core. This is primarily because core is primarily a teaching ISA. One of the best parts about RiscV is that you can teach a freshman level architecture class or a senior level chip building project with an ISA that is actually used. Anything powerful to run (a non built from source manually) linux will support a profile that bundles all the commonly needed instructions to be fast.

hackyhacky 8mo ago
> One of the best parts about RiscV is that you can teach a freshman level architecture class or a senior level chip building project with an ISA that is actually used. Same could be said of MIPS. My understanding is the RISC-V raison d'etre is rather avoidance of patented/copywritten designs.
- adgjlsfhk1 8mo ago
  the avoidance of patent/copyright is critical for (legally) having students design their own chips. MIPS was pretty good (and widely used) for teaching assembly, but pretty bad for teaching a class where students design chips
  - userbinator 8mo ago
    MIPS patents have long expired too (and incidentally for any other CPU released prior to 2006), so that's a moot point.
  - musicale 8mo ago
    This is largely contradicted by the (pre RISC-V) MIPS editions of Patterson & Hennessy, Harris & Harris, etc., which teach you how to design a MIPS datapath (at the gate level.) Regarding silicon implementations, consider that 1) you can synthesize it from HDL/RTL designs using modern CAD tools, and 2) MIPS was originally designed to be simple enough for grad students to implement with the primitive CAD tools of the 1980s (basically semi-manual layout).
- musicale 8mo ago
  As you indicate, MIPS was widely used in computer architecture courses and textbooks, including pre-RISC-V editions of Patterson & Hennessy (Computer Organization & Design) and Harris & Harris (Digital Design and Computer Architecture. In spite of the currently mediocre RISC-V implementations, RISC-V seems to have more of a future and isn't clouded by ISA IP issues, as you note.
jacquesm 8mo ago
Bit manipulation instructions are part and parcel of any curriculum that teaches CPU architecture. They are the basic building blocks for many more complex instructions. https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html I can see quite a few items on that list that imnsho should have been included in the core and for the life of me I can't see the rationale behind leaving them out. Even the most basic 8 bit CPU had various shifts and rolls baked in.
- rwmj 8mo ago
  This is the reason behind the profiles like RVA23 which include bitmanip, vector and a large number of other extensions. Real chips coming very soon will all be RVA23.
  - jacquesm 8mo ago
    Neat. I can't wait to get my hands on a devboard.
    - NekkoDroid 8mo ago
      The earlierst I know of coming is the SpaceMit K3, which Sipeed will have dev boards for.
    - statusfailed 8mo ago
      The Milk-V Jupiter 2 (coming out in April) is RV23 too
      - jacquesm 8mo ago
        Nice board but very low on max RAM.
        rwmj 8mo ago
        The Milk-V Titan (https://milkv.io/titan https://milkv.io/titan) can take up to 64GB which is fine considering the number of cores and the cost of RAM. If you needed and could afford more RAM you'd be better off distributing the work across more than one board.
Joker_vD 8mo ago
> This is primarily because core is primarily a teaching ISA. That doesn't necessarily make it all that great for industrial use, does it? > One of the best parts about RiscV is that you can teach a freshman level architecture class or a senior level chip building project with an ISA that is actually used. You can also do that with Intel MCS-51 (aka 8051) or even i960. And again, having an ISA easily implementable "on a knee" by a fresh graduate doesn't says anything about its other technical merits other than being "easily implementable (when done in the most primitive way possible)".

hackyhacky 8mo ago

> One of the best parts about RiscV is that you can teach a freshman level architecture class or a senior level chip building project with an ISA that is actually used. Same could be said of MIPS. My understanding is the RISC-V raison d'etre is rather avoidance of patented/copywritten designs.

adgjlsfhk1 8mo ago
the avoidance of patent/copyright is critical for (legally) having students design their own chips. MIPS was pretty good (and widely used) for teaching assembly, but pretty bad for teaching a class where students design chips
- userbinator 8mo ago
  MIPS patents have long expired too (and incidentally for any other CPU released prior to 2006), so that's a moot point.
- musicale 8mo ago
  This is largely contradicted by the (pre RISC-V) MIPS editions of Patterson & Hennessy, Harris & Harris, etc., which teach you how to design a MIPS datapath (at the gate level.) Regarding silicon implementations, consider that 1) you can synthesize it from HDL/RTL designs using modern CAD tools, and 2) MIPS was originally designed to be simple enough for grad students to implement with the primitive CAD tools of the 1980s (basically semi-manual layout).
musicale 8mo ago
As you indicate, MIPS was widely used in computer architecture courses and textbooks, including pre-RISC-V editions of Patterson & Hennessy (Computer Organization & Design) and Harris & Harris (Digital Design and Computer Architecture. In spite of the currently mediocre RISC-V implementations, RISC-V seems to have more of a future and isn't clouded by ISA IP issues, as you note.

jacquesm 8mo ago

Bit manipulation instructions are part and parcel of any curriculum that teaches CPU architecture. They are the basic building blocks for many more complex instructions. https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html I can see quite a few items on that list that imnsho should have been included in the core and for the life of me I can't see the rationale behind leaving them out. Even the most basic 8 bit CPU had various shifts and rolls baked in.

rwmj 8mo ago
This is the reason behind the profiles like RVA23 which include bitmanip, vector and a large number of other extensions. Real chips coming very soon will all be RVA23.
- jacquesm 8mo ago
  Neat. I can't wait to get my hands on a devboard.
  - NekkoDroid 8mo ago
    The earlierst I know of coming is the SpaceMit K3, which Sipeed will have dev boards for.
  - statusfailed 8mo ago
    The Milk-V Jupiter 2 (coming out in April) is RV23 too
    - jacquesm 8mo ago
      Nice board but very low on max RAM.
      - rwmj 8mo ago
        The Milk-V Titan (https://milkv.io/titan https://milkv.io/titan) can take up to 64GB which is fine considering the number of cores and the cost of RAM. If you needed and could afford more RAM you'd be better off distributing the work across more than one board.

Joker_vD 8mo ago

> This is primarily because core is primarily a teaching ISA. That doesn't necessarily make it all that great for industrial use, does it? > One of the best parts about RiscV is that you can teach a freshman level architecture class or a senior level chip building project with an ISA that is actually used. You can also do that with Intel MCS-51 (aka 8051) or even i960. And again, having an ISA easily implementable "on a knee" by a fresh graduate doesn't says anything about its other technical merits other than being "easily implementable (when done in the most primitive way possible)".