5 ms·

Also the bit manipulation extension wasn't part of the core. So things like bit rotation is slow for no good reason, if you want portable code. Why? Who knows.

fidotron 8mo ago
The fact the Hazard3 designer ended up creating an extension to resolve related oddities was kind of astonishing. Why did it fall to them to do it? Impressive that he did, but it shouldn't have been necessary.
- rllj 8mo ago
  Which extension is that?
  - mjmas 8mo ago
    An extension he calls Xh3bextm. For extracting multiple bits from bitfields. https://wren.wtf/hazard3/doc/#extension-xh3bextm-section https://wren.wtf/hazard3/doc/#extension-xh3bextm-section There are also four other custom extensions implemented.
    - wren6991 8mo ago
      This extension wasn't strictly necessary but it makes decode of Arm instructions faster in the bootrom's Arm emulator.
adgjlsfhk1 8mo ago
> Also the bit manipulation extension wasn't part of the core. This is primarily because core is primarily a teaching ISA. One of the best parts about RiscV is that you can teach a freshman level architecture class or a senior level chip building project with an ISA that is actually used. Anything powerful to run (a non built from source manually) linux will support a profile that bundles all the commonly needed instructions to be fast.
- hackyhacky 8mo ago
  > One of the best parts about RiscV is that you can teach a freshman level architecture class or a senior level chip building project with an ISA that is actually used. Same could be said of MIPS. My understanding is the RISC-V raison d'etre is rather avoidance of patented/copywritten designs.
  - adgjlsfhk1 8mo ago
    the avoidance of patent/copyright is critical for (legally) having students design their own chips. MIPS was pretty good (and widely used) for teaching assembly, but pretty bad for teaching a class where students design chips
    - userbinator 8mo ago
      MIPS patents have long expired too (and incidentally for any other CPU released prior to 2006), so that's a moot point.
    - musicale 8mo ago
      This is largely contradicted by the (pre RISC-V) MIPS editions of Patterson & Hennessy, Harris & Harris, etc., which teach you how to design a MIPS datapath (at the gate level.) Regarding silicon implementations, consider that 1) you can synthesize it from HDL/RTL designs using modern CAD tools, and 2) MIPS was originally designed to be simple enough for grad students to implement with the primitive CAD tools of the 1980s (basically semi-manual layout).
  - musicale 8mo ago
    As you indicate, MIPS was widely used in computer architecture courses and textbooks, including pre-RISC-V editions of Patterson & Hennessy (Computer Organization & Design) and Harris & Harris (Digital Design and Computer Architecture. In spite of the currently mediocre RISC-V implementations, RISC-V seems to have more of a future and isn't clouded by ISA IP issues, as you note.
- jacquesm 8mo ago
mort96 8mo ago
Do you typically care about portability to the degree that you want the same machine code to execute on both a Linux box and a microcontroller? Why?

fidotron 8mo ago

The fact the Hazard3 designer ended up creating an extension to resolve related oddities was kind of astonishing. Why did it fall to them to do it? Impressive that he did, but it shouldn't have been necessary.

rllj 8mo ago
Which extension is that?
- mjmas 8mo ago
  An extension he calls Xh3bextm. For extracting multiple bits from bitfields. https://wren.wtf/hazard3/doc/#extension-xh3bextm-section https://wren.wtf/hazard3/doc/#extension-xh3bextm-section There are also four other custom extensions implemented.
  - wren6991 8mo ago
    This extension wasn't strictly necessary but it makes decode of Arm instructions faster in the bootrom's Arm emulator.

adgjlsfhk1 8mo ago

> Also the bit manipulation extension wasn't part of the core. This is primarily because core is primarily a teaching ISA. One of the best parts about RiscV is that you can teach a freshman level architecture class or a senior level chip building project with an ISA that is actually used. Anything powerful to run (a non built from source manually) linux will support a profile that bundles all the commonly needed instructions to be fast.

hackyhacky 8mo ago
> One of the best parts about RiscV is that you can teach a freshman level architecture class or a senior level chip building project with an ISA that is actually used. Same could be said of MIPS. My understanding is the RISC-V raison d'etre is rather avoidance of patented/copywritten designs.
- adgjlsfhk1 8mo ago
  the avoidance of patent/copyright is critical for (legally) having students design their own chips. MIPS was pretty good (and widely used) for teaching assembly, but pretty bad for teaching a class where students design chips
  - userbinator 8mo ago
    MIPS patents have long expired too (and incidentally for any other CPU released prior to 2006), so that's a moot point.
  - musicale 8mo ago
    This is largely contradicted by the (pre RISC-V) MIPS editions of Patterson & Hennessy, Harris & Harris, etc., which teach you how to design a MIPS datapath (at the gate level.) Regarding silicon implementations, consider that 1) you can synthesize it from HDL/RTL designs using modern CAD tools, and 2) MIPS was originally designed to be simple enough for grad students to implement with the primitive CAD tools of the 1980s (basically semi-manual layout).
- musicale 8mo ago
  As you indicate, MIPS was widely used in computer architecture courses and textbooks, including pre-RISC-V editions of Patterson & Hennessy (Computer Organization & Design) and Harris & Harris (Digital Design and Computer Architecture. In spite of the currently mediocre RISC-V implementations, RISC-V seems to have more of a future and isn't clouded by ISA IP issues, as you note.
jacquesm 8mo ago

mort96 8mo ago

Do you typically care about portability to the degree that you want the same machine code to execute on both a Linux box and a microcontroller? Why?