No, if that were the case, then Google would have made GPUs + NN cores vs TPUs. There's far more microarchitectural complexity in GPUs that actually isn't effi

No, if that were the case, then Google would have made GPUs + NN cores vs TPUs. There's far more microarchitectural complexity in GPUs that actually isn't efficient for NN structures. "Systolic array" actually means something more specific than "repeated structures on a die." Again, I'd suggest referencing the various HotChips presentations. It's a really interesting topic area. Or the original TPU v1 paper for the basics.