the behaviour is quite typical for any MESI style cache coherence system (i.e. most if not all of them). A specific microarchitecture might alleviate this a bi

the behaviour is quite typical for any MESI style cache coherence system (i.e. most if not all of them). A specific microarchitecture might alleviate this a bit with lower latency cross-core communication, but the solution (using a single naive RW lock to protect the cache) is inherently non-scalable.