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One interesting observation is that successful RISC CPUs dont have a super simple ISA anymore. At least not in the frontend. MIPS was notorious for having a si
by throwa356262 8mo ago
One interesting observation is that successful RISC CPUs dont have a super simple ISA anymore. At least not in the frontend.
MIPS was notorious for having a simple ISA and RISCV is trying to mimick that to some extent.
But look at thumb2 for example and you will see complex encodings and even variable instruction width.
- kjs3 8mo agoBack in the day, Alpha and HPPA were commonly used as examples of 'with all this extra stuff is it still RISC?'. These days, I think the CISC/RISC divide is largely an historical artifact.
- throwa356262 8mo agoI think the idea of simplicity is still relevant, but the problem is not as simple as (no pun) having a certain look to your ISA anymore. ISA transformed to something unrecognisable 2-3 steps into the pipeline, the rest of the CPU doesn't see much of the ISA. Maybey we should abandon "reduced instruction set" and instead evaluate how ISA is suitable for out of order execution or speculative execution or backtracking and so on
- kjs3 8mo agoFair. Personally, I think the idea of simplicity is still relevant for pedagogy (as it always is), but one you rope in 'suitable for out of order execution or speculative execution or backtracking and so on' as criteria, 'simple' is harder to achieve (at least for practical commercial designs). YMMV.
- userbinator 8mo agoARM64 looked like an exercise in "what can we squeeze into a 32-bit instruction" the first time I examined it in detail; the various "load/store register pair" instructions are a great example of this. I would consider it even more difficult to decode than x86, and yet it's still nowhere near as dense as Thumb2 nor x86.
- dmitrygr 8mo agoBut thumb2 is dead. “Successful RISC CPUs” is aarch64. No thumb2.