3 ms·
> and now lets count the number of companies that can put up the capital for tape-out: amd, intel, arm, nvidia, meta, aws, google chips, apple, and lets say plu
by RealityVoid 8mo ago
> and now lets count the number of companies that can put up the capital for tape-out: amd, intel, arm, nvidia, meta, aws, google chips, apple, and lets say plus 50 for fintechs, startups, and other 'smaller' orgs.
And basically anyone who has a job in tech [1] or someone who just pulled their salary out of the ATM has enough money to do a tapeout with the cash in their hand [2] or chinese students for basically free[3]. Of course, for _some_ scopes of tapeout. These are older nodes and you have limited area. But you might not need anything fancy for your design.
The rest of the post, I think has a bunch of misunderstandings or wrong facts, but I don't work in the field, (ish) so I might be as clueless as you and I need to get back to my day job so I won't try countering you just yet.
[1] https://wafer.space/ https://wafer.space/
[2] https://app.tinytapeout.com/calculator?tiles=1&pcbs=1 https://app.tinytapeout.com/calculator?tiles=1&pcbs=1
[3] https://ysyx.oscc.cc/docs/en/ https://ysyx.oscc.cc/docs/en/
- cfd456 8mo ago3 designers per silicon org is a ludicrous underestimate
- RealityVoid 8mo agoYes, one of the ludicrous statements. I would invite him to take a look at OpenTitan for example and see how many designers work there on that thing.