You also have to account for register renaming, which basically means each pipeline may have their own register set invisible to the others. And that IIRC depen

You also have to account for register renaming, which basically means each pipeline may have their own register set invisible to the others. And that IIRC depends on how the instruction scheduler is planning the the execution and SRAM space needed, therefore calculating the total SRAM space that the registers taken would be far more realistic.