I used Verilog a little bit in college, while studying for my EE degree. It didn't seem like a bad language. It was a weird blend of register transfer-level s

I used Verilog a little bit in college, while studying for my EE degree. It didn't seem like a bad language. It was a weird blend of register transfer-level stuff and C-like pseudocode stuff. It sounds like Verilog fell prey to the C++ philosophy of language design-- just keep adding anything that sounds remotely like a good idea to the core language. If it interacts poorly with what's already there, that's just too bad. Unfortunately, new programming languages are NOT a good startup idea, in any field. Also, if people are paying 5 and 6 figures for tools in SystemVerilog, change is going to be slow.