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What, you don't think systemverilog is the cat's meow? </sarcasm> I've been in the industry for about 15 years. I agree the languages are horrible. The tools

What, you don't think systemverilog is the cat's meow? </sarcasm> I've been in the industry for about 15 years. I agree the languages are horrible. The tools can be buggy, but I don't feel they are all horrible. There are open source verilog and vhdl simulators out there, although I haven't used them yet [1]. They could be a good starting point for tool improvement. It mentions synthesis as well, but anything practical for hacking would have to target FPGAs and that means vendor tools have to be involved. While the hardware implementation languages could stand improvement, verification is the largest consumer of resources right now. Being able to work in something like python or clojure for testbenches would be really interesting. [1] http://iverilog.icarus.com

jgw 14y ago
re: buggy vs horrible tools A matter of degrees, I guess. They're certainly improving, but we run into bugs and missing core language features in all three major vendors. I work for a consulting company, and we switch simulators and coding styles from one gig to another, so that may amplify my perception of bugginess. But just as examples, in the last couple of years, my coworkers and I have discovered: - a case where one simulator gets the xor of a two-state and a four-state logic vector wrong. - a case where another simulator converts from 4-state to 2-state value with the wrong result. - one of the simulators doesn't implement a single-precision floating point type Those are pretty fundamental bugs - not the class of bug I expect to find in a tool that has been in the wild for 5 or 6 years and costs more than my car for a single one-year license. And we've found many, many more less-blatant ones.
- DigitalJack 14y ago
  Yes, that is pretty bad. It seems like things have been slipping lately. I wish the vendors would stop adding new features and just fix what they've already got.
krupan 14y ago
icarus is slow and has no intention of supporting SystemVerilog, last time I checked. Other interesting projects: http://pyhvl.sourceforge.net/ http://pyhvl.sourceforge.net/ http://www.myhdl.org/doku.php/start http://www.myhdl.org/doku.php/start I couldn't get pyhvl to work, reported a bug, and got no response. For verification there should have been effort expended on creating libraries for existing high-level software languages and on interop between those languages and simulators, not on creating our own iffy language (SystemVerilog), and then a huge library to work around all the deficiencies and impedance mismatches between the language and the problems we are trying to solve (UVM).

jgw 14y ago

re: buggy vs horrible tools A matter of degrees, I guess. They're certainly improving, but we run into bugs and missing core language features in all three major vendors. I work for a consulting company, and we switch simulators and coding styles from one gig to another, so that may amplify my perception of bugginess. But just as examples, in the last couple of years, my coworkers and I have discovered: - a case where one simulator gets the xor of a two-state and a four-state logic vector wrong. - a case where another simulator converts from 4-state to 2-state value with the wrong result. - one of the simulators doesn't implement a single-precision floating point type Those are pretty fundamental bugs - not the class of bug I expect to find in a tool that has been in the wild for 5 or 6 years and costs more than my car for a single one-year license. And we've found many, many more less-blatant ones.

DigitalJack 14y ago
Yes, that is pretty bad. It seems like things have been slipping lately. I wish the vendors would stop adding new features and just fix what they've already got.

krupan 14y ago

icarus is slow and has no intention of supporting SystemVerilog, last time I checked. Other interesting projects: http://pyhvl.sourceforge.net/ http://pyhvl.sourceforge.net/ http://www.myhdl.org/doku.php/start http://www.myhdl.org/doku.php/start I couldn't get pyhvl to work, reported a bug, and got no response. For verification there should have been effort expended on creating libraries for existing high-level software languages and on interop between those languages and simulators, not on creating our own iffy language (SystemVerilog), and then a huge library to work around all the deficiencies and impedance mismatches between the language and the problems we are trying to solve (UVM).