I'd heartily recommend to make the most of co-op opportunities if you can. I learned way more in co-op than I ever did in school. I suppose it's harder these

I'd heartily recommend to make the most of co-op opportunities if you can. I learned way more in co-op than I ever did in school. I suppose it's harder these days, as resources are stretched further so it's difficult for staff to allocate spare cycles for mentoring. It's unfortunately myopic, as we really need to invest more in guys like you for our future. Real board-level skills are difficult to acquire on your own. I've only done a little - and that was last millenium - but a lot of it is a black art: rules of thumb here and there about what works, what doesn't - and they're best learned as an apprentice to someone who's been doing it a while. VHDL is probably a cleaner language than Verilog/SystemVerilog, but it's used less in industry - at least in ASIC designs. There are free Verilog compilers/simulators (Icarus Verilog being a common one); there are probably no free SV implementations. Not sure what the status of free VHDL is. There are probably decent cheap options for development boards from Altera, Xilinx and co. Feel free to drop me a line if you want to discuss further - email in profile.