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It's quite curious how hardware design lost its cachet. When I was in Computer Engineering at Waterloo (class of '98), many of my classmates were vying for coo

by jgw 14y ago

It's quite curious how hardware design lost its cachet. When I was in Computer Engineering at Waterloo (class of '98), many of my classmates were vying for coop jobs in FPGA, ASIC or board-level design. I happened to be one of the lucky ones and it set me on a path to a career in ASIC verification. Today when I look around at my industry, it's downright shocking how little young blood there is around. The youngest ASIC guy I've met in the last 6 or 7 years had a Master's and three years experience - and we all regarded him as the newbie. Only in the last few months have we seen the occasional new-grad's resume cross our threshold. I'd not yet call it a trend, but I hope it becomes one. We have horrible languages, horrible libraries, horrible tools - a huge, shaky mess of infrastructure built on technologies stretched far beyond what they were originally built for - and it's so deeply entrenched that few of my colleagues seem to recognize it. We really need a new generation of fresh perspectives to shake us all up. Let's hope it is indeed a new renaissance that Mr. Graham heralds.

Irishsteve 14y ago
Post a link to the most mainstream tool please. Someone might try to change that world.
- ccoggins 14y ago
  Some of the tools we used in my computer engineering curriculum were HDL Designer from Mentor Graphics and some tools from Xylinx that were similar. If I remember correctly the reps from Caterpillar said they invested in HDL Designer pretty heavily as it was used widely there. I mention Caterpillar specifically because their world headquarters was about an hour and a half down the road and they recruited pretty heavily from UIUC. HDL Designer was cool but it was pretty outdated looking even 5 years ago when I was at school. It was all motif running on Sparc Solaris boxes.
- jgw 14y ago
  While I admire your moxy, you need to understand that a full suite of tools we use to get ASICs designed, verified, laid out and ready for fab cost 5 or 6 figures per license, depending on what you're doing. The very use of the tools themselves, is subject to non-disclosure agreements. So are the details of their pricing. I do think the status quo will be radically reshaped by an external force one day, but thinking one is going to mount an assault without knowing who the three main EDA vendors are - let alone without real-world ASIC experience - is quixotic. It is also not obvious to me how the economics of a viable competitor would actually work. [EDIT: I hope this didn't come across as excessively abrasive. You are quite right - it's an industry that needs shaking up, but its not obvious how to do it. Fresh faces and new ideas would help us at least realize that there is a problem]
  - waterlesscloud 14y ago
    Could you talk a little about what the major shortcomings of the current players are?
    - jgw 14y ago
      My biggest gripe would be with the abomination of a language we have for functional design and verification, SystemVerilog. - It has been developed without public discussion, now that the IEEE has shut down their mailing lists to non-paying entities and persons - The steering committee are bright, well-meaning individuals... who don't appear to have any language design experience between them, and whose knowledge of programming languages appear to be limited to Verilog, Java and a daring dash of Tcl. They have never seen a feature they didn't think was worth adding as new syntax. - It retains backward compatibility with Verilog, which was a cool hack in 1983. - It basically looks like Java with a whole bunch of additional (inconsistent) syntax for stuff that should probably be in a standard library, but... - It doesn't have a standard library - Oh, and by Java, I mean Java as it was in 1995. Or at least, it will have sort of the same feature set, once they add interface inheritance - later this year. Yup, 2012. - Its metaprogramming facilities are weaker than ANSI C, which is why most large ASIC shops end up brewing their own metalanguage syntax, usually by having embedded snippets of Perl or Tcl. - And this inexpressive, crippled language somehow has a spawling mess of a spec that runs a whopping 1200+ pages. The entire thing is a train-wreck.
      - cmccabe 14y ago
        I used Verilog a little bit in college, while studying for my EE degree. It didn't seem like a bad language. It was a weird blend of register transfer-level stuff and C-like pseudocode stuff. It sounds like Verilog fell prey to the C++ philosophy of language design-- just keep adding anything that sounds remotely like a good idea to the core language. If it interacts poorly with what's already there, that's just too bad. Unfortunately, new programming languages are NOT a good startup idea, in any field. Also, if people are paying 5 and 6 figures for tools in SystemVerilog, change is going to be slow.
btilly 14y ago
I have a friend who has been trying to convince me that it is feasible to create a language that can let a general purpose programmer write useful software and "compile" it down to a FPGA to run really, really fast. (He has a lot of specific thoughts that I won't share about what such a language should look like.) In principle he thinks that it should be possible to compile such a language down to an ASIC representation, but that would only make sense for very high volume runs. (He's specifically interested in software to run financial models, so those would not be high volume runs.) He makes sense to me, but I have no idea what practical difficulties there would be. But does something like this sound doable in principle from your point of view?
- jgw 14y ago
  There are a number of solutions that do that kind of thing to a degree - and they are improving. For certain types of designs, you can actually compile fairly unrestricted C and C++ into gates that are faster and lower gate-count than hand-coded Verilog designs. Your friend's domain might well be one of them. I think you need some specialized knowledge to use this existing generation of tools, but having never used such tools, I couldn't quantify that. I'm also not sure how well these tools perform on arbitrary hardware designs. But no - I certainly don't think he's out to lunch.
  - btilly 14y ago
    The problem is that C and C++ do not implicitly parallelize well. To get maximum bang for the bunk you want to extract lots of parallelism. Which requires a different kind of language. The interesting flip side is that if you design for easy parallelism, you are better able to take advantage of multiple cores in standard CPUs. Also you can then turn it around and also distribute the same program across a cluster of commodity hardware on the cloud. But yes, the toolchain matters. A lot.
    - ableal 14y ago
      > maximum bang for the bunk That ranks up with "rear-window defrogger" and "string-loaded door" in my collection of amusing typos ...
alanctgardner2 14y ago
I'm in Comp Eng. at the University of Ottawa right now, and I'm having a hell of a time getting any hands on experience with FPGAs or board-level design. I worked for one company on Co-op which was good enough to let me try to layout a simple board, but I'd simply never seen the best practices at work, and nobody really had the time to teach. I found VHDL really interesting, but I've only had about two classes worth, and I haven't really has a hobby project. I've though about picking up an Altera dev board and emulating an old computer architecture; is that the kind of practice you think would be worthwhile? Do you have any tips about learning board design and what kinds of projects/hardware are good to get started on?
- jgw 14y ago
  I'd heartily recommend to make the most of co-op opportunities if you can. I learned way more in co-op than I ever did in school. I suppose it's harder these days, as resources are stretched further so it's difficult for staff to allocate spare cycles for mentoring. It's unfortunately myopic, as we really need to invest more in guys like you for our future. Real board-level skills are difficult to acquire on your own. I've only done a little - and that was last millenium - but a lot of it is a black art: rules of thumb here and there about what works, what doesn't - and they're best learned as an apprentice to someone who's been doing it a while. VHDL is probably a cleaner language than Verilog/SystemVerilog, but it's used less in industry - at least in ASIC designs. There are free Verilog compilers/simulators (Icarus Verilog being a common one); there are probably no free SV implementations. Not sure what the status of free VHDL is. There are probably decent cheap options for development boards from Altera, Xilinx and co. Feel free to drop me a line if you want to discuss further - email in profile.
- pnathan 14y ago
  If you want to check out VHDL in depth, you'll want to get this if you can: http://www.digilentinc.com/ http://www.digilentinc.com/ I've used them in digital design courses, they are pretty awesome. Xilinx, however, is eldritch.
  - alanctgardner2 14y ago
krupan 14y ago
"We have horrible languages, horrible libraries, horrible tools - a huge, shaky mess of infrastructure built on technologies stretched far beyond what they were originally built for - and it's so deeply entrenched that few of my colleagues seem to recognize it. We really need a new generation of fresh perspectives to shake us all up." I have somewhat recently transitioned from embedded software to verification, and you have hit the nail right on the head. We should talk.
- DigitalJack 14y ago
  What, you don't think systemverilog is the cat's meow? </sarcasm> I've been in the industry for about 15 years. I agree the languages are horrible. The tools can be buggy, but I don't feel they are all horrible. There are open source verilog and vhdl simulators out there, although I haven't used them yet [1]. They could be a good starting point for tool improvement. It mentions synthesis as well, but anything practical for hacking would have to target FPGAs and that means vendor tools have to be involved. While the hardware implementation languages could stand improvement, verification is the largest consumer of resources right now. Being able to work in something like python or clojure for testbenches would be really interesting. [1] http://iverilog.icarus.com
  - jgw 14y ago
    re: buggy vs horrible tools A matter of degrees, I guess. They're certainly improving, but we run into bugs and missing core language features in all three major vendors. I work for a consulting company, and we switch simulators and coding styles from one gig to another, so that may amplify my perception of bugginess. But just as examples, in the last couple of years, my coworkers and I have discovered: - a case where one simulator gets the xor of a two-state and a four-state logic vector wrong. - a case where another simulator converts from 4-state to 2-state value with the wrong result. - one of the simulators doesn't implement a single-precision floating point type Those are pretty fundamental bugs - not the class of bug I expect to find in a tool that has been in the wild for 5 or 6 years and costs more than my car for a single one-year license. And we've found many, many more less-blatant ones.
etrautmann 14y ago
This is addressing a different level of hardware. I don't think the primary drivers of a hardware revolution (new tools, cheap and rapid prototyping, etc) extend to ASIC design. As a recently graduated Masters EE student, none of my fellow students considered VLSI and chip design to be a new or hot area or seriously considered it as a career path. I don't doubt that there's plenty of innovation there, but it's rightly or wrongly perceived as being less sexy than other subfields of EE.

by jgw 14y ago

Irishsteve 14y ago

Post a link to the most mainstream tool please. Someone might try to change that world.

ccoggins 14y ago
Some of the tools we used in my computer engineering curriculum were HDL Designer from Mentor Graphics and some tools from Xylinx that were similar. If I remember correctly the reps from Caterpillar said they invested in HDL Designer pretty heavily as it was used widely there. I mention Caterpillar specifically because their world headquarters was about an hour and a half down the road and they recruited pretty heavily from UIUC. HDL Designer was cool but it was pretty outdated looking even 5 years ago when I was at school. It was all motif running on Sparc Solaris boxes.
jgw 14y ago
While I admire your moxy, you need to understand that a full suite of tools we use to get ASICs designed, verified, laid out and ready for fab cost 5 or 6 figures per license, depending on what you're doing. The very use of the tools themselves, is subject to non-disclosure agreements. So are the details of their pricing. I do think the status quo will be radically reshaped by an external force one day, but thinking one is going to mount an assault without knowing who the three main EDA vendors are - let alone without real-world ASIC experience - is quixotic. It is also not obvious to me how the economics of a viable competitor would actually work. [EDIT: I hope this didn't come across as excessively abrasive. You are quite right - it's an industry that needs shaking up, but its not obvious how to do it. Fresh faces and new ideas would help us at least realize that there is a problem]
- waterlesscloud 14y ago
  Could you talk a little about what the major shortcomings of the current players are?
  - jgw 14y ago
    My biggest gripe would be with the abomination of a language we have for functional design and verification, SystemVerilog. - It has been developed without public discussion, now that the IEEE has shut down their mailing lists to non-paying entities and persons - The steering committee are bright, well-meaning individuals... who don't appear to have any language design experience between them, and whose knowledge of programming languages appear to be limited to Verilog, Java and a daring dash of Tcl. They have never seen a feature they didn't think was worth adding as new syntax. - It retains backward compatibility with Verilog, which was a cool hack in 1983. - It basically looks like Java with a whole bunch of additional (inconsistent) syntax for stuff that should probably be in a standard library, but... - It doesn't have a standard library - Oh, and by Java, I mean Java as it was in 1995. Or at least, it will have sort of the same feature set, once they add interface inheritance - later this year. Yup, 2012. - Its metaprogramming facilities are weaker than ANSI C, which is why most large ASIC shops end up brewing their own metalanguage syntax, usually by having embedded snippets of Perl or Tcl. - And this inexpressive, crippled language somehow has a spawling mess of a spec that runs a whopping 1200+ pages. The entire thing is a train-wreck.
    - cmccabe 14y ago
      I used Verilog a little bit in college, while studying for my EE degree. It didn't seem like a bad language. It was a weird blend of register transfer-level stuff and C-like pseudocode stuff. It sounds like Verilog fell prey to the C++ philosophy of language design-- just keep adding anything that sounds remotely like a good idea to the core language. If it interacts poorly with what's already there, that's just too bad. Unfortunately, new programming languages are NOT a good startup idea, in any field. Also, if people are paying 5 and 6 figures for tools in SystemVerilog, change is going to be slow.

btilly 14y ago

I have a friend who has been trying to convince me that it is feasible to create a language that can let a general purpose programmer write useful software and "compile" it down to a FPGA to run really, really fast. (He has a lot of specific thoughts that I won't share about what such a language should look like.) In principle he thinks that it should be possible to compile such a language down to an ASIC representation, but that would only make sense for very high volume runs. (He's specifically interested in software to run financial models, so those would not be high volume runs.) He makes sense to me, but I have no idea what practical difficulties there would be. But does something like this sound doable in principle from your point of view?

jgw 14y ago
There are a number of solutions that do that kind of thing to a degree - and they are improving. For certain types of designs, you can actually compile fairly unrestricted C and C++ into gates that are faster and lower gate-count than hand-coded Verilog designs. Your friend's domain might well be one of them. I think you need some specialized knowledge to use this existing generation of tools, but having never used such tools, I couldn't quantify that. I'm also not sure how well these tools perform on arbitrary hardware designs. But no - I certainly don't think he's out to lunch.
- btilly 14y ago
  The problem is that C and C++ do not implicitly parallelize well. To get maximum bang for the bunk you want to extract lots of parallelism. Which requires a different kind of language. The interesting flip side is that if you design for easy parallelism, you are better able to take advantage of multiple cores in standard CPUs. Also you can then turn it around and also distribute the same program across a cluster of commodity hardware on the cloud. But yes, the toolchain matters. A lot.
  - ableal 14y ago
    > maximum bang for the bunk That ranks up with "rear-window defrogger" and "string-loaded door" in my collection of amusing typos ...

alanctgardner2 14y ago

I'm in Comp Eng. at the University of Ottawa right now, and I'm having a hell of a time getting any hands on experience with FPGAs or board-level design. I worked for one company on Co-op which was good enough to let me try to layout a simple board, but I'd simply never seen the best practices at work, and nobody really had the time to teach. I found VHDL really interesting, but I've only had about two classes worth, and I haven't really has a hobby project. I've though about picking up an Altera dev board and emulating an old computer architecture; is that the kind of practice you think would be worthwhile? Do you have any tips about learning board design and what kinds of projects/hardware are good to get started on?

jgw 14y ago
I'd heartily recommend to make the most of co-op opportunities if you can. I learned way more in co-op than I ever did in school. I suppose it's harder these days, as resources are stretched further so it's difficult for staff to allocate spare cycles for mentoring. It's unfortunately myopic, as we really need to invest more in guys like you for our future. Real board-level skills are difficult to acquire on your own. I've only done a little - and that was last millenium - but a lot of it is a black art: rules of thumb here and there about what works, what doesn't - and they're best learned as an apprentice to someone who's been doing it a while. VHDL is probably a cleaner language than Verilog/SystemVerilog, but it's used less in industry - at least in ASIC designs. There are free Verilog compilers/simulators (Icarus Verilog being a common one); there are probably no free SV implementations. Not sure what the status of free VHDL is. There are probably decent cheap options for development boards from Altera, Xilinx and co. Feel free to drop me a line if you want to discuss further - email in profile.
pnathan 14y ago
If you want to check out VHDL in depth, you'll want to get this if you can: http://www.digilentinc.com/ http://www.digilentinc.com/ I've used them in digital design courses, they are pretty awesome. Xilinx, however, is eldritch.
- alanctgardner2 14y ago

krupan 14y ago

"We have horrible languages, horrible libraries, horrible tools - a huge, shaky mess of infrastructure built on technologies stretched far beyond what they were originally built for - and it's so deeply entrenched that few of my colleagues seem to recognize it. We really need a new generation of fresh perspectives to shake us all up." I have somewhat recently transitioned from embedded software to verification, and you have hit the nail right on the head. We should talk.

DigitalJack 14y ago
What, you don't think systemverilog is the cat's meow? </sarcasm> I've been in the industry for about 15 years. I agree the languages are horrible. The tools can be buggy, but I don't feel they are all horrible. There are open source verilog and vhdl simulators out there, although I haven't used them yet [1]. They could be a good starting point for tool improvement. It mentions synthesis as well, but anything practical for hacking would have to target FPGAs and that means vendor tools have to be involved. While the hardware implementation languages could stand improvement, verification is the largest consumer of resources right now. Being able to work in something like python or clojure for testbenches would be really interesting. [1] http://iverilog.icarus.com
- jgw 14y ago
  re: buggy vs horrible tools A matter of degrees, I guess. They're certainly improving, but we run into bugs and missing core language features in all three major vendors. I work for a consulting company, and we switch simulators and coding styles from one gig to another, so that may amplify my perception of bugginess. But just as examples, in the last couple of years, my coworkers and I have discovered: - a case where one simulator gets the xor of a two-state and a four-state logic vector wrong. - a case where another simulator converts from 4-state to 2-state value with the wrong result. - one of the simulators doesn't implement a single-precision floating point type Those are pretty fundamental bugs - not the class of bug I expect to find in a tool that has been in the wild for 5 or 6 years and costs more than my car for a single one-year license. And we've found many, many more less-blatant ones.

etrautmann 14y ago

This is addressing a different level of hardware. I don't think the primary drivers of a hardware revolution (new tools, cheap and rapid prototyping, etc) extend to ASIC design. As a recently graduated Masters EE student, none of my fellow students considered VLSI and chip design to be a new or hot area or seriously considered it as a career path. I don't doubt that there's plenty of innovation there, but it's rightly or wrongly perceived as being less sexy than other subfields of EE.