https://github.com/antmicro/wireshark-pcie-dissector https://github.com/antmicro/wireshark-pcie-dissector or https://github.com/sora/wireshark-pcie/blob/master

https://github.com/antmicro/wireshark-pcie-dissector https://github.com/antmicro/wireshark-pcie-dissector or https://github.com/sora/wireshark-pcie/blob/master/plugins/pcie.lua https://github.com/sora/wireshark-pcie/blob/master/plugins/p... (The PCIe wire format consists of TLPs and DLLPs. Context: https://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-2 https://xillybus.com/tutorials/pci-express-tlp-pcie-primer-t... )