> making it easy to compare execution strategies and choose the best one Once your CPU has pipelining and out-of-order execution (which they will, of speed is

> making it easy to compare execution strategies and choose the best one Once your CPU has pipelining and out-of-order execution (which they will, of speed is an issue), that easy gets out, no matter what instruction set your CPU uses. Fast code also often needs to be adjusted depending on the size and timing of various caches. That’s no different with RISC-V. I also expect that RISC-V will have warts in its instruction set, if it doesn’t already have them. For example, there’s the idea of instruction fusion, where the CPU treats a pair of instructions as a single one. If you’re writing assembler, whether your specific CPU fuses an instruction pair can affect what the fastest code is.