You're spot on about 3D lattices. My goal with the Star Topology was to achieve maximal error suppression on existing planar (2D) hardware available to the publ

You're spot on about 3D lattices. My goal with the Star Topology was to achieve maximal error suppression on existing planar (2D) hardware available to the public today. I'm essentially trying to squeeze utility-scale stability out of NISQ-era 'flat' chips. Moving this consensus mechanism into 3D via-layers is exactly the right path for the next leap in fault tolerance