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Is it just "some upcoming chips" inventing their own extensions? Or is this a standardized ARM extension? Basically, will writing against these upcoming chips
by mort96 10mo ago
Is it just "some upcoming chips" inventing their own extensions? Or is this a standardized ARM extension?
Basically, will writing against these upcoming chips mean writing one implementation for Qualcomm, one implementation for Rockchip, one implementation for Samsung, etc? Or will it just require one implementation for the standard ARM "switch to total store ordering memory model" extension
- snvzz 10mo ago>Is it just "some upcoming chips" inventing their own extensions? Or is this a standardized ARM extension? RISC-V has an official ratified extension for TSO, and a work-in-progress one for dynamic switching between RISC-V's standard memory model and TSO.
- Findecanor 10mo agoI'm sorry, I meant RISC-V, not ARM. So far the RISC-V standard has specified behaviour under the TSO memory model and a flag in the ELF header for code that has been compiled for TSO. There is not yet any ratified extension for dynamic switching of memory model but I'd expect anything vendor-specific to be wrapped behind a Linux syscall.