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I agree with everything you're saying, I just think the 'obvious point' is one that's papered over in the public discourse a lot because it's not exciting. It
by jbooth 14y ago
I agree with everything you're saying, I just think the 'obvious point' is one that's papered over in the public discourse a lot because it's not exciting.
It is interesting why they don't scale linearly and I agree that it's probably a combination of memory bus contention and/or the chip itself being a little slower.
The whole bulldozer thing seemed like a marketing stunt rather than thoughtful pursuit of higher performance to me. Given the frequency and cost of cache miss rates, Intel HT seems to get the same work done on fewer watts.
- marshray 14y agoI really don't think AMD would have bet their next generation of chips on something they believed was a marketing stunt. Once the upcoming chip changes get explained to the Marketing Department, however, maybe it kinda starts to sound like Marketing.
- frozenport 14y agoIntel HT is often disabled on HPC clusters due to performance problems. Also many people refer to the IL as a 8 core CPU due to the problems mentioned above. Much like not using the HT, many codes disable half the AMD chip.
- jbooth 14y agoYeah, but it's really only on highly-optimized cache-coherent vector/matrix math that it's a problem. On just about every other piece of software, it works great. I feel like AMD saw the benchmarks available for matrix math and went for it, rather than thinking about what real-world performance profiles looked like.