4 ms·
A quick clarification: on Apple Silicon there is no user-space equivalent of x86 CLFLUSH, so the benchmark can’t force cold caches between runs. Cache behavior
by user_timo 10mo ago
A quick clarification: on Apple Silicon there is no user-space equivalent of x86 CLFLUSH, so the benchmark can’t force cold caches between runs. Cache behavior is inferred via buffer sizing, warm-up, and steady-state measurements.