3 ms·
AArch64 also zeroes the upper 32 bits of the destination register when you use a 32 bit instruction.
by 201984 10mo ago
AArch64 also zeroes the upper 32 bits of the destination register when you use a 32 bit instruction.
- flykespice 10mo agoI'm curious, why is that? I know x86-64 zeroes the upper part of the register for backwards compability and improve instruction cache (no need for REX prefix), but AArch64 is unclear for me.
- School-Cotton 10mo agoI don't know either, but why wouldn't backwards compatibility apply to aarch64? It too is based on a pre-existing 32-bit architecture.
- Narishma 10mo agoI don't think it's backwards compatible the same way x86-64 is.
- 201984 10mo agoIt's to break dependencies for register renaming. If you have an instruction like mov w5, w6 // move low 32 bits of register 6 into low 32 bits of register 5 This instruction only depends on the value of register 6. If instead it of zeroing the upper half it left it unchanged, then it would depend on w6 and also the previous value of register 5. That would constrain the renamer and consequently out-of-order execution.
- zeuxcg 10mo agoYou really want to avoid a dependency on prior content of the destination register, to allow renaming and maximize out of order scheduling.