3 ms·
I don't think decode is really the hard part; if you're JITting at all it's pretty easy. The difficulties arise where the semantics of the target and the host d
by pm215 14y ago
I don't think decode is really the hard part; if you're JITting at all it's pretty easy. The difficulties arise where the semantics of the target and the host don't match up. For instance, emulating a strong-memory-model architecture like x86 on a weak-memory-model architecture like ARM requires a pile of explicit memory barriers if you're going to handle multi-threaded binaries. Emulating atomic memory accesses might also be tricky. Differences in floating point semantics (like x86's 80-bit format or just different choices of IEEE implementation specifics) are also painful: QEMU takes the slow-but-safe option of doing all the floating point emulation in software (ie using integer arithmetic) to ensure bit-for-bit accuracy. None of these pain points is really related to the instruction decoding.
- koenigdavidmj 14y agoAccording to Herb Sutter at [1], ARMv8 will support a couple new ops to support sequentially consistent memory access. 1: http://herbsutter.com/2012/08/02/strong-and-weak-hardware-memory-models/ http://herbsutter.com/2012/08/02/strong-and-weak-hardware-me...