3 ms·
Because for timing-sensitive code, those are important. If a variable is really a register, cache-based timing attacks just don't happen, because there is no ca
by thyristan 11mo ago
Because for timing-sensitive code, those are important. If a variable is really a register, cache-based timing attacks just don't happen, because there is no cache in between.
- saagarjha 11mo agoI don’t think register has ever guaranteed that.