3 ms·
I have not seen that yet DDR5, I think the signal integrity requirements are too high now to even have unused pads open. Most sticks don’t appear to have many t
by buildbot 11mo ago
I have not seen that yet DDR5, I think the signal integrity requirements are too high now to even have unused pads open. Most sticks don’t appear to have many traces at all on the top/bottom sides, just big power/ground planes.
Also with DDR5 each stick is actually 2 channels so you get 2 extra dies.
- b112 11mo agoThere's some new half assed ECC type of RAM, not sure the name. Was reading a series of displeased posts about it. Can't seem to find it now.
- lmz 11mo agoOn die ECC for DDR5. Which corrects locally but does not signal the host or deal with data between the die and the CPU.
- b112 11mo agoThanks, drove me bananas trying to find that again.
- herewulf 11mo agoPresumably this is being marketed indistinguishably from regular ECC RAM? If so, that's terrible news. It was already difficult enough to find ECC RAM for "workstation" class machines (i.e.: High end, non-server CPUs that support ECC such as AMD Threadripper).
- buildbot 11mo agoIt's not - ECC RAM still means real, between the RAM and CPU ECC. It's literally an extra 8 bits per channels, for an extra 16 bits per dim. 40 bits vs 32.