3 ms·
yeah that is correct. The m series chips can turn on total store ordering memory model solely for Rosetta. There's also some hardware extensions to arm to suppo
by fooblaster 11mo ago
yeah that is correct. The m series chips can turn on total store ordering memory model solely for Rosetta. There's also some hardware extensions to arm to support x86 condition codes in the hardware because it's way more instruction efficient that way.
- astrange 11mo agoIf you mean FEAT_FlagM, that's standard in ARMv8.4. (There's also FlagM2 and AFP that are optional.) The JavaScript instruction is cooler though. https://developer.arm.com/documentation/dui0801/g/A64-Floating-point-Instructions/FJCVTZS https://developer.arm.com/documentation/dui0801/g/A64-Floati...
- gorkish 11mo agoRISC is dead; long live RISC
- sgerenser 11mo agoThe latter is now an optional feature in the mainstream Arm ISA now (FEAT_FlagM and FEAT_FlagM2). Similarly the “alternate floating point mode” that Apple uses to match nuances of x86 FP semantics is a standard architectural feature as well. The TSO option though is Apples own thing.