I wonder what happened to hardware transactional memory. Your CPU caches already keep track of which core is keeping which line in its cache and whether they ha

I wonder what happened to hardware transactional memory. Your CPU caches already keep track of which core is keeping which line in its cache and whether they have modified it via the MESI protocol: https://en.wikipedia.org/wiki/MESI_protocol https://en.wikipedia.org/wiki/MESI_protocol So it has most of the hardware to support transactional memory, only it's not exposed to the user. Intel had their own version, but it turned out it was buggy, so they disabled it and never put it in any subsequent CPU so that was that.