3 ms·

Is this 30Mhz value per chip, or per memory channel? Would it be possible to increase total random access throughput by adding more chips to a channel and pipe

by codex 14y ago

Is this 30Mhz value per chip, or per memory channel? Would it be possible to increase total random access throughput by adding more chips to a channel and pipelining more requests?

Tuna-Fish 14y ago
It's per memory cell. And that's what all modern memory does. Ignoring chop (afaik, no modern widely used memory controller makes use of it), the smallest request you can make from a 64-bit DDR3 stick is 64 bytes. All those 512 bits are accessed in parallel, and when done, sent over the memory bus over 8 bus transfers. While the controller is waiting for those bits to become available, you can issue commands to different banks within the same chip. (And in fact must do so to get anywhere close to the nominal bandwidth). Modern memory controllers interleave requests both between banks of the same chip and between different chips on the same channel.
ajross 14y ago
It's per "bank". Chips often are partitioned into multiple banks, each with its own row/column array. This gives some parallelism, because an access to one bank won't invalidate the already-loaded row in the others (reads of bits in the same row as the previous one are faster because they are stored/cached in digital logic -- this is why sequential access to DRAM is faster than random acccess). Obviously the width of the DRAM bus itself is a parallelism design: fundamentally DRAM is always "one bit wide", you get wider busses by using multiple devices and feeding them the same commands. And you can get even more parallelism by using more than one DRAM channel. Intel Desktop CPUs have 2x 64 bit channels, the LGA2011 server parts have 4x64, Apple's new A6 made news this week by moving to a 2x32 bit design. But note that those are all bandwidth improvements. They don't do anything to the time it takes to get a bit out of an idle DRAM part. DRAM latency is largely fixed in the modern world, until we find a different way of storing bits.
- tisme 14y ago
  Or switch to more expensive but faster SRAM.

by codex 14y ago

Is this 30Mhz value per chip, or per memory channel? Would it be possible to increase total random access throughput by adding more chips to a channel and pipelining more requests?

Tuna-Fish 14y ago

It's per memory cell. And that's what all modern memory does. Ignoring chop (afaik, no modern widely used memory controller makes use of it), the smallest request you can make from a 64-bit DDR3 stick is 64 bytes. All those 512 bits are accessed in parallel, and when done, sent over the memory bus over 8 bus transfers. While the controller is waiting for those bits to become available, you can issue commands to different banks within the same chip. (And in fact must do so to get anywhere close to the nominal bandwidth). Modern memory controllers interleave requests both between banks of the same chip and between different chips on the same channel.

ajross 14y ago

It's per "bank". Chips often are partitioned into multiple banks, each with its own row/column array. This gives some parallelism, because an access to one bank won't invalidate the already-loaded row in the others (reads of bits in the same row as the previous one are faster because they are stored/cached in digital logic -- this is why sequential access to DRAM is faster than random acccess). Obviously the width of the DRAM bus itself is a parallelism design: fundamentally DRAM is always "one bit wide", you get wider busses by using multiple devices and feeding them the same commands. And you can get even more parallelism by using more than one DRAM channel. Intel Desktop CPUs have 2x 64 bit channels, the LGA2011 server parts have 4x64, Apple's new A6 made news this week by moving to a 2x32 bit design. But note that those are all bandwidth improvements. They don't do anything to the time it takes to get a bit out of an idle DRAM part. DRAM latency is largely fixed in the modern world, until we find a different way of storing bits.

tisme 14y ago
Or switch to more expensive but faster SRAM.