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> Or put differently, why bake the CPU instruction sets into the chips? There is more to a CPU instruction set than just instruction encodings. For instance, x

by cesarb 1y ago

> Or put differently, why bake the CPU instruction sets into the chips? There is more to a CPU instruction set than just instruction encodings. For instance, x86 has flags which are updated (sometimes partially) by a lot of instructions, and a stronger memory model (TSO), while RISC-V has its own peculiar ideas on the result of an integer division by zero. > What Apple has shown is that emulating x86 can actually rival or be faster than a natively running x86 chip. AFAIK, Apple has special support in its processors for emulating x86. It has a hardware mode which emulates the x86 memory model, and IIRC also has something in hardware to help emulate the x86 flags register.

snvzz 1y ago
>while RISC-V has its own peculiar ideas on the result of an integer division by zero. Yeah, it does. Its architects knew that it is cheaper to, when necessary, check and branch if the divisor is zero than it is to deal with exceptions. Thus that hardware budget can instead be used for making the chip faster and more power efficient.
cogman10 1y ago
> It has a hardware mode which emulates the x86 memory model, and IIRC also has something in hardware to help emulate the x86 flags register. AFAIK, the memory model is the main missing piece. And it seems like it's certainly something that could be implemented separately. IMO, it's something the ARM group could (and probably should) easily add into the platform. The flags register is a minor thing that's pretty easy to pull off. Most of the x86 instructions that mess with the flags have direct ARM instructions. The ones that don't can easily be emulated by burning a register and maintaining the flags in said register when needs be. I think the other important thing to note is that while x86 has a wealth of exotic functions that do wild things, a lot of those instructions aren't generated by any modern compiler. Not saying you can't find a stray `ENTER`/`LEAVE` instruction in old software, it's just not likely. That significantly cuts down on weird instructions doing wild things harming performance. A quick google about what apple did to support x86 flags is they added undocumented bits to their own flags register to help support 8080 instructions.

by cesarb 1y ago

snvzz 1y ago

>while RISC-V has its own peculiar ideas on the result of an integer division by zero. Yeah, it does. Its architects knew that it is cheaper to, when necessary, check and branch if the divisor is zero than it is to deal with exceptions. Thus that hardware budget can instead be used for making the chip faster and more power efficient.

cogman10 1y ago

> It has a hardware mode which emulates the x86 memory model, and IIRC also has something in hardware to help emulate the x86 flags register. AFAIK, the memory model is the main missing piece. And it seems like it's certainly something that could be implemented separately. IMO, it's something the ARM group could (and probably should) easily add into the platform. The flags register is a minor thing that's pretty easy to pull off. Most of the x86 instructions that mess with the flags have direct ARM instructions. The ones that don't can easily be emulated by burning a register and maintaining the flags in said register when needs be. I think the other important thing to note is that while x86 has a wealth of exotic functions that do wild things, a lot of those instructions aren't generated by any modern compiler. Not saying you can't find a stray `ENTER`/`LEAVE` instruction in old software, it's just not likely. That significantly cuts down on weird instructions doing wild things harming performance. A quick google about what apple did to support x86 flags is they added undocumented bits to their own flags register to help support 8080 instructions.