4 ms·
In case anyone needs a minimal CPU implementation in 65 lines of Verilog: https://people.csail.mit.edu/ebakke/fic/ https://people.csail.mit.edu/ebakke/fic/ http
by eirikbakke 11mo ago
In case anyone needs a minimal CPU implementation in 65 lines of Verilog:
https://people.csail.mit.edu/ebakke/fic/ https://people.csail.mit.edu/ebakke/fic/
https://people.csail.mit.edu/ebakke/fic/code/Fic.v https://people.csail.mit.edu/ebakke/fic/code/Fic.v
(I wonder if it would convert cleanly to a redstone circuit...)
- lpribis 11mo agoThis compiler does not support sequential logic, meaning no flip flops/registers.