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RISC-V is still at the point where open-source implementations (in rtl) are faster than purchasable proprietary ones (in silicon). XiangShan is currently the f

RISC-V is still at the point where open-source implementations (in rtl) are faster than purchasable proprietary ones (in silicon). XiangShan is currently the fastest open-source CPU implementation: https://github.com/OpenXiangShan/XiangShan https://github.com/OpenXiangShan/XiangShan uarch slides: https://tutorial.xiangshan.cc/hpca25/slides/20250302-HPCA25-2-Microarchitecture.pdf https://tutorial.xiangshan.cc/hpca25/slides/20250302-HPCA25-... uarch slides with WIP features: https://tutorial.xiangshan.cc/micro25/slides/Microarchitecture%20Design%20Philosophy.pdf https://tutorial.xiangshan.cc/micro25/slides/Microarchitectu...

kragen 1y ago
Do you expect that to change at some point?
- rwmj 1y ago
  I've just seen a demo of a very high performance RISC-V chip (actual silicon) that'll blow the doors off other implementations. Under NDA of course. Actually available for pre-order, take a look at the UltraRISC DP-1000 (unrelated to the chip above).
  - 0x000xca0xfe 1y ago
    Can you share any details? Like potential year of release?
    - rwmj 1y ago
      That's actually the most NDA thing, since companies don't want to be held to a release date. However the fact they have fully functional engineering samples running in their offices now is very encouraging.
  - kragen 1y ago
    Excellent! But probably open-source implementations will also continue to improve.
- camel-cdr 1y ago
  Yes, but keep in mind that I'm purposfully comparing development RTL on the open-source side with finished silicon product on the proprietary side. Many companies have production ready/fully verified IP that are much faster than XiangShan, but they haven't taped out and productized it yet. E.g. Tenstorrent Ascalon IP is available and at 21 SPECint2006/GHz. They want to release a lower clocked devboard on TSMC 12nm in 2026 Q2. XiangShan is currently at 15 SPECint2006/GHz, but are targeting 22 SPECint2006/GHz in the next iteration, that is currently in the works. Well have to see who gets there first. The inherent gap between RTL design and final product may be large enough that open-source RTL can keep up in terms of IPC, if XiangShan continues their momentum. But I think open-source trailing 1-3 years is a more realistic long term outcome.

kragen 1y ago

Do you expect that to change at some point?

rwmj 1y ago
I've just seen a demo of a very high performance RISC-V chip (actual silicon) that'll blow the doors off other implementations. Under NDA of course. Actually available for pre-order, take a look at the UltraRISC DP-1000 (unrelated to the chip above).
- 0x000xca0xfe 1y ago
  Can you share any details? Like potential year of release?
  - rwmj 1y ago
    That's actually the most NDA thing, since companies don't want to be held to a release date. However the fact they have fully functional engineering samples running in their offices now is very encouraging.
- kragen 1y ago
  Excellent! But probably open-source implementations will also continue to improve.
camel-cdr 1y ago
Yes, but keep in mind that I'm purposfully comparing development RTL on the open-source side with finished silicon product on the proprietary side. Many companies have production ready/fully verified IP that are much faster than XiangShan, but they haven't taped out and productized it yet. E.g. Tenstorrent Ascalon IP is available and at 21 SPECint2006/GHz. They want to release a lower clocked devboard on TSMC 12nm in 2026 Q2. XiangShan is currently at 15 SPECint2006/GHz, but are targeting 22 SPECint2006/GHz in the next iteration, that is currently in the works. Well have to see who gets there first. The inherent gap between RTL design and final product may be large enough that open-source RTL can keep up in terms of IPC, if XiangShan continues their momentum. But I think open-source trailing 1-3 years is a more realistic long term outcome.