4 ms·
Berkeley Out-of-Order RISC-V Processor (Boom) (2020)
- phkahler 11mo agoThe latest version seems to be Sonic Boom: https://github.com/riscv-boom/riscv-boom https://github.com/riscv-boom/riscv-boom But this project seems to have stagnated with one significant commit in the last year.
- huyage 11mo agoIf I want to do systems research that needs a simple and synthesizable RISC-V design, what are some good options? BOOM seems to be pretty complicated and I don't really need the out-of-order execution. I also want to be able to run it on a cheap FPGA, something like Artix A7.
- daedalus- 11mo agoTry neorv32: https://github.com/stnolting/neorv32 https://github.com/stnolting/neorv32
- huyage 11mo agoThanks. Looks good! Are you aware of any 64-bit options?
- jhallenworld 11mo agoWish it was Verilog or SystemVerilog..
- rwmj 11mo agoRocket-chip is widely used (https://github.com/chipsalliance/rocket-chip https://github.com/chipsalliance/rocket-chip). It can fit on smaller FPGAs. If you want something very tiny and completely understandable, and don't mind that it's 32 bit, then PicoRV32 (https://github.com/YosysHQ/picorv32 https://github.com/YosysHQ/picorv32).
- dmitrygr 11mo agohttps://github.com/Wren6991/Hazard3 https://github.com/Wren6991/Hazard3 this one is well tested in real life and works well (it is the RV core in RP2350)
- panick21 11mo agoThis is what the OpenHW Foundaiton is for. Providing well verified cores for people who just need a core. They are based on the original Pulp Cores from the ETH Zürich and Unviersity of Bolongia. See: https://openhwfoundation.org/ https://openhwfoundation.org/ Or because its part of OpenTitan, Ibex sees a lot of development: https://github.com/lowRISC/ibex https://github.com/lowRISC/ibex
- drob518 11mo agoThere’s a nice list of open source cores here: https://github.com/suryakantamangaraj/AwesomeRISC-VResources https://github.com/suryakantamangaraj/AwesomeRISC-VResources
- kragen 11mo agoClaire Wolf's PicoRV32 seems to get a lot of "simple and synthesizable RISC-V design to run on a cheap FPGA" use, although that's more typically for much cheaper FPGA's than an Artix A7, like an iCE40. SeRV is even cheaper and simpler but much slower. Graeme Smecher’s RVC-first "Minimax" is almost as simple as SeRV but not nearly as slow. I haven't tried any of them, though, so take this with a Himalayan salt lamp.
- jhallenworld 11mo agoI've been getting tremendous use out of PicoRV32- it works, it's tiny, and for many use cases ("management plane") you just don't need much speed. I work around its slowness by providing things like relatively large communication buffers in the FPGA. I use it in "execute in place" mode from external SPI-flash (the FPGA's config flash), but with an instruction cache. It can do floating point via emulation which is handy for printf. I've been meaning to update my toolbox to at least a pipelined processor of some sort (to up the IPC rate to at least 1), but so far just had no strong need. For applications that really need CPU power, I use SoC FPGAs like Zynq.
- camel-cdr 11mo agoRISC-V is still at the point where open-source implementations (in rtl) are faster than purchasable proprietary ones (in silicon). XiangShan is currently the fastest open-source CPU implementation: https://github.com/OpenXiangShan/XiangShan https://github.com/OpenXiangShan/XiangShan uarch slides: https://tutorial.xiangshan.cc/hpca25/slides/20250302-HPCA25-2-Microarchitecture.pdf https://tutorial.xiangshan.cc/hpca25/slides/20250302-HPCA25-... uarch slides with WIP features: https://tutorial.xiangshan.cc/micro25/slides/Microarchitecture%20Design%20Philosophy.pdf https://tutorial.xiangshan.cc/micro25/slides/Microarchitectu...
- kragen 11mo agoDo you expect that to change at some point?
- rwmj 11mo agoI've just seen a demo of a very high performance RISC-V chip (actual silicon) that'll blow the doors off other implementations. Under NDA of course. Actually available for pre-order, take a look at the UltraRISC DP-1000 (unrelated to the chip above).
- 0x000xca0xfe 11mo agoCan you share any details? Like potential year of release?
- rwmj 11mo agoThat's actually the most NDA thing, since companies don't want to be held to a release date. However the fact they have fully functional engineering samples running in their offices now is very encouraging.
- kragen 11mo agoExcellent! But probably open-source implementations will also continue to improve.
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