3 ms·
That's called 4k aliasing. 4K aliasing occurs when you store one memory location, then load from another memory location which is 4KB offset from original.
by srcmax 1y ago
That's called 4k aliasing.
4K aliasing occurs when you store one memory location, then load from another memory location which is 4KB offset from original.
- jmalicki 1y ago(and if it is not apparent to some readers, most modern x86-based systems use 64 byte cache line sizes, which is sort of analogous to disk block size - quite a few memory operations tend to happen in 64 byte chunks under the covers - the ones that don't are "special")
- nabla9 1y agoTo my knowledge all x86 based systems and ARM and Qualcomm designed chips all use 64 byte cache lines. Apple's M2 uses 128-byte cache line.
- themafia 1y agoWould you expect different performance with 2M page sizes? Is this a TLB issue or just a fundamental hardware issue?
- gpderetta 1y agoApparently these ~4k spikes are showing up only on AMD, and not on Intel, which is the one known to suffer from the 4k aliasing problem. I wonder if it has to do with a non-ideal implementation of virtual address resolution for the next page.