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You've also got the problem of cosmic radiation flipping bits. Your fault tolerant architecture probably mitigates this with redundancy, with the extra servers
by notahacker 1y ago
You've also got the problem of cosmic radiation flipping bits. Your fault tolerant architecture probably mitigates this with redundancy, with the extra servers again eating into the purported advantages of extra solar power. Dealing with the PITA of single event upsets is something developers of edge data processing software in space put up with to avoid the latency issues that data clouds in space introduce
- preisschild 1y agoI wonder if "normal" RDIMM ECC would be enough to mitigate most of those radiation bit-flipping issues. If so it wouldn't really make a difference to earth-based servers since most enterprise servers use RDIMM ECC too
- eptcyka 1y agoYou'll get bitflips elsewhere besides just in RAM. A bitflip in L1 or L3 cache will be propagated to your DIMM and noone will be the wiser.
- zamadatix 1y agoI thought server CPUs already handled this? E.g. for Epyc https://moorinsightsstrategy.com/wp-content/uploads/2017/05/AMD-EPYC-Brings-New-RAS-Capability-by-Moor-Insights-and-Strategy.pdf https://moorinsightsstrategy.com/wp-content/uploads/2017/05/... > Because caches hold the most recent and most relevant data to the current processing, it is critical that this data be accurate. To enable this, AMD has designed EPYC with multiple tiers of cache protection. The level 1 data cache includes SEC-DED ECC, which can detect two-bit errors and correct single-bit errors. Through parity and retry, L1 data cache tag errors and L1 instruction cache errors are automatically corrected. The L2 and L3 caches are extended even further with the ability to correct double errors and detect triple errors.
- LtdJorge 1y agoThose do ECC already
- ls612 1y agoWhat about the registers?
- yencabulator 1y agoWhat about the ALU/FPU/TPU itself?
- shrubble 1y agoSun Microsystems famously had this problem with their servers using the UltraSPARC II chips, with cache SRAM that didn’t have ECC. Later versions of their processors had ECC added.
- btown 1y agoIn all seriousness, if AI models can handle quantization, they can handle some flipped bits from time to time! There are probably some fascinating papers to be written around how to choose which layers in an LLM architecture could benefit more than others from redundant computation in a high-radiation environment.
- kibwen 1y agoBrilliant, to turn up the model temperature we just hinge open the shielding. I call dibs on the patent!
- lawlessone 1y agoOk, has anyone patented chips with radioactive source glued to them? For "true" randomness. If it not i want dibs on it.
- DontBreakAlex 1y agohttps://en.wikipedia.org/wiki/Hardware_random_number_generator https://en.wikipedia.org/wiki/Hardware_random_number_generat... > and even the nuclear decay (due to practical considerations the latter, as well as the atmospheric noise, is not viable except for fairly restricted applications or online distribution services)
- notahacker 1y agoyeah, I think the space weather experts would have fun statistically analysing the single-event-upset RNG :)