2 ms·
This article from the same site goes into the Infinity Cache design in a bit more detail: https://chipsandcheese.com/p/amds-cdna-3-compute-architecture https://
by noelwelsh 1y ago
This article from the same site goes into the Infinity Cache design in a bit more detail: https://chipsandcheese.com/p/amds-cdna-3-compute-architecture https://chipsandcheese.com/p/amds-cdna-3-compute-architectur...
The summary is that it's a cache attached to the memory controllers, rather than the CPUs, so it doesn't have to worry about cache coherency so much. This could be useful for shared memory parallelism.
- joelthelion 1y agoThank you!
- jbreitbart 1y agoSince it is attached to the memory controller, one could argue that it is truly the final level of the cache hierarchy and the term infinity is not only a marketing term.
- ot 1y agoBut then you could add another level of slower (but still faster than RAM) and larger cache. So it is after all the CPU caches, but the first of all the memory caches. A more mathematically correct name would be L_omega.
- p_l 1y agoIBM Power8 and Power9 used Centaur chips which had similar "last level cache" onboard. Because it is last level before the actual ram chips, no coherency involved.
- MisterTea 1y agoSounds a bit like a tightly coupled memory (TCM) in an embedded CPU; Fast single cycle RAM shared across the system.
- ignaloidas 1y agoThis is quite exactly the opposite of TCM in fact