4 ms·

I don't quite get it. What's so special about having 32MB of cache? Why is it called "infinity"?

noelwelsh 1y ago
This article from the same site goes into the Infinity Cache design in a bit more detail: https://chipsandcheese.com/p/amds-cdna-3-compute-architecture https://chipsandcheese.com/p/amds-cdna-3-compute-architectur... The summary is that it's a cache attached to the memory controllers, rather than the CPUs, so it doesn't have to worry about cache coherency so much. This could be useful for shared memory parallelism.
- joelthelion 1y ago
  Thank you!
- jbreitbart 1y ago
  Since it is attached to the memory controller, one could argue that it is truly the final level of the cache hierarchy and the term infinity is not only a marketing term.
  - ot 1y ago
    But then you could add another level of slower (but still faster than RAM) and larger cache. So it is after all the CPU caches, but the first of all the memory caches. A more mathematically correct name would be L_omega.
- p_l 1y ago
  IBM Power8 and Power9 used Centaur chips which had similar "last level cache" onboard. Because it is last level before the actual ram chips, no coherency involved.
- MisterTea 1y ago
  Sounds a bit like a tightly coupled memory (TCM) in an embedded CPU; Fast single cycle RAM shared across the system.
  - ignaloidas 1y ago
    This is quite exactly the opposite of TCM in fact
pixelpoet 1y ago
What makes Intel's SMT implementation "hyper"? What makes Mario "Super"? It's just marketing.
- themafia 1y ago
  > What makes Mario "Super"? The Super Mushroom power-up.
  - ahofmann 1y ago
    SCNR: What makes the Mushroom power-up "Super"?
    - fruitworks 1y ago
      It's got what mario craves
      - askl 1y ago
        Electrolytes?
- arjvik 1y ago
  Hyperthreading is technically a level above superscalar?
- dripdry45 1y ago
  Apparently, Mario actually was the super for the building that they were in. He was not super, he was the super (supervisor) fixing stuff
  - motorest 1y ago
    > Apparently, Mario actually was the super for the building that they were in. He was not super, he was the super (supervisor) fixing stuff +1 insightful.
phire 1y ago
AMD named their memory fabric "infinity fabric" for marketing reasons. So when they developed their memory attached cache solution (which lives in the memory fabric, unlike a traditional cache), the obvious marketing name is "infinity cache" The main advantage of a memory attached cache is that it's cheaper than a regular cache, and can even be put on a seperate die, allowing you to have much more of it. AMDs previous memory fabric from the early 2000s was called "Hyper Transport", which has a confusing overlap with Intel's Hyper Threading, but I think AMD actually bet intel to the name by a few years.
- typpilol 1y ago
  How's latency vs a traditional?
  - Tuna-Fish 1y ago
    It has a higher latency than AMD's L2 caches, but similar compared to Nvidia's L2. [0] I think AMD might be ditching it for the next gen in exchange for growing the L2's, because the lower latency is beneficial to ray tracing. [0]: https://substackcdn.com/image/fetch/$s_!LHJo!,f_auto,q_auto:good,fl_progressive:steep/https%3A%2F%2Fsubstack-post-media.s3.amazonaws.com%2Fpublic%2Fimages%2F925f51b0-7857-42d4-8980-eefdef474d8a_1600x897.png https://substackcdn.com/image/fetch/$s_!LHJo!,f_auto,q_auto:...
    - ColonelPhantom 1y ago
      Not sure if ditching infinity cache/L3 for a bigger L2 would make sense. It seems at least plausible to me that growing the L2 cache that much would make its latency worse, thus losing most of what has been gained. In the image you linked, Nvidia's L2 latency is like twice as high as AMD's! Keep in mind that the 'big' desktop chips have bigger caches too. The L2 on a 5080 and 'L3' on a 9070 XT are both 64 MB. Additionally, AMD has already been growing the L2, going to 8 MB on the 9070 XT vs. 4 MB on the 7800 XT and 6800 XT.
      - Tuna-Fish 1y ago

This article from the same site goes into the Infinity Cache design in a bit more detail: https://chipsandcheese.com/p/amds-cdna-3-compute-architecture https://chipsandcheese.com/p/amds-cdna-3-compute-architectur... The summary is that it's a cache attached to the memory controllers, rather than the CPUs, so it doesn't have to worry about cache coherency so much. This could be useful for shared memory parallelism.

joelthelion 1y ago
Thank you!
jbreitbart 1y ago
Since it is attached to the memory controller, one could argue that it is truly the final level of the cache hierarchy and the term infinity is not only a marketing term.
- ot 1y ago
  But then you could add another level of slower (but still faster than RAM) and larger cache. So it is after all the CPU caches, but the first of all the memory caches. A more mathematically correct name would be L_omega.
p_l 1y ago
IBM Power8 and Power9 used Centaur chips which had similar "last level cache" onboard. Because it is last level before the actual ram chips, no coherency involved.
MisterTea 1y ago
Sounds a bit like a tightly coupled memory (TCM) in an embedded CPU; Fast single cycle RAM shared across the system.
- ignaloidas 1y ago
  This is quite exactly the opposite of TCM in fact

pixelpoet 1y ago

What makes Intel's SMT implementation "hyper"? What makes Mario "Super"? It's just marketing.

themafia 1y ago
> What makes Mario "Super"? The Super Mushroom power-up.
- ahofmann 1y ago
  SCNR: What makes the Mushroom power-up "Super"?
  - fruitworks 1y ago
    It's got what mario craves
    - askl 1y ago
      Electrolytes?
arjvik 1y ago
Hyperthreading is technically a level above superscalar?
dripdry45 1y ago
Apparently, Mario actually was the super for the building that they were in. He was not super, he was the super (supervisor) fixing stuff
- motorest 1y ago
  > Apparently, Mario actually was the super for the building that they were in. He was not super, he was the super (supervisor) fixing stuff +1 insightful.

phire 1y ago

AMD named their memory fabric "infinity fabric" for marketing reasons. So when they developed their memory attached cache solution (which lives in the memory fabric, unlike a traditional cache), the obvious marketing name is "infinity cache" The main advantage of a memory attached cache is that it's cheaper than a regular cache, and can even be put on a seperate die, allowing you to have much more of it. AMDs previous memory fabric from the early 2000s was called "Hyper Transport", which has a confusing overlap with Intel's Hyper Threading, but I think AMD actually bet intel to the name by a few years.

typpilol 1y ago
How's latency vs a traditional?
- Tuna-Fish 1y ago
  It has a higher latency than AMD's L2 caches, but similar compared to Nvidia's L2. [0] I think AMD might be ditching it for the next gen in exchange for growing the L2's, because the lower latency is beneficial to ray tracing. [0]: https://substackcdn.com/image/fetch/$s_!LHJo!,f_auto,q_auto:good,fl_progressive:steep/https%3A%2F%2Fsubstack-post-media.s3.amazonaws.com%2Fpublic%2Fimages%2F925f51b0-7857-42d4-8980-eefdef474d8a_1600x897.png https://substackcdn.com/image/fetch/$s_!LHJo!,f_auto,q_auto:...
  - ColonelPhantom 1y ago
    Not sure if ditching infinity cache/L3 for a bigger L2 would make sense. It seems at least plausible to me that growing the L2 cache that much would make its latency worse, thus losing most of what has been gained. In the image you linked, Nvidia's L2 latency is like twice as high as AMD's! Keep in mind that the 'big' desktop chips have bigger caches too. The L2 on a 5080 and 'L3' on a 9070 XT are both 64 MB. Additionally, AMD has already been growing the L2, going to 8 MB on the 9070 XT vs. 4 MB on the 7800 XT and 6800 XT.
    - Tuna-Fish 1y ago