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This is an oft-repeated misunderstanding. DDR5 memory uses error correcting codes internally to correct on-die errors, but this does not defend against errors
by timschmidt 1y ago
This is an oft-repeated misunderstanding. DDR5 memory uses error correcting codes internally to correct on-die errors, but this does not defend against errors on busses between the DIMM and memory controller. For that the old scheme of extra chips to store additional ECC data is still the only way.
- hedora 1y agoIt actually does protect against errors on access, but support is optional. Also, some vendors use a non-optimal hamming code that fails to notice some double bit errors (if I remember right).
- wtallis 1y ago> It actually does protect against errors on access, but support is optional. Can you explain how exactly the on-die ECC capability can help protect data in transit? What is the optional functionality you're referring to, if not the traditional sideband ECC achieved by adding another chip's worth of data lines to every channel?