4 ms·

Every event loop is subject to the blocked-due-to-long-running-computation issue. It bites ...

• asveikau 1y ago
  The same is true if you're repeatedly polling an atomic boolean in an event loop.
  • CamperBob2 1y ago
    How so? It takes only a couple of machine cycles to poll a boolean. (And what other kind of boolean is there, besides atomic? It's either true or it's false, and if nothing can set it back to false once it goes true, I don't see the hazard. It's a CPU, not an FPGA.)
    • kbolino 1y ago
      The type is named atomic, but atomicity is not its only useful property. The atomic types also give control over the memory ordering, defaulting to sequentially consistent (seq_cst, the strongest). Without memory order guarantees enforced by memory barriers, a write to the boolean in thread A is not guaranteed to be observed by thread B. That matters both after initialization--where thread A sets the boolean to false but thread B may observe true, false, or invalid--and also after the transition--where thread B may fail to observe that the boolean has flipped from false to true. [edit: I'm not sure the above reasoning actually matters; as stated already by parent, "It's a CPU, not an FPGA"; modern multicore shared-memory CPUs have coherent caches]
      • CamperBob2 1y ago
        Well, it'll be observed the next time through the loop. If that matters, then it's true that this technique isn't desirable.
        • manwe150 1y ago
          Without atomic, the compiler won’t bother with there being a next time and just infinite loop (in the old days, you’d mark it volatile instead)
          • CamperBob2 1y ago
            True enough, but volatile still works, of course.
      • adwn 1y ago
        > Without memory order guarantees enforced by memory barriers, a write to the boolean in thread A is not guaranteed to be observed by thread B. No, that's not correct. Memory ordering doesn't influence how fast a write is propagated to other cores, that's what cache coherency is for. Memory ordering of an access only matters in relation to accesses on other memory locations. There's a great introduction to this topic by Mara Bos: https://marabos.nl/atomics/memory-ordering.html https://marabos.nl/atomics/memory-ordering.html
        • kbolino 1y ago
          Indeed. I started to figure this out, hence my edit. Thanks for the link. There are hypothetical, historical, and special-purpose architectures which don't have cache coherency (or implement it differently enough to matter here), but for all practical purposes, it seems that all modern, general-purpose architectures implement it.
    • mattgreenrocks 1y ago
      It’s free on x86 for relaxed ordering, which is sufficient for this use case.