> You are, of course, right, although I'd say that it's fairly unusual for the "sequential execution of CPU instructions" abstraction to leak. On x86. x86 and

> You are, of course, right, although I'd say that it's fairly unusual for the "sequential execution of CPU instructions" abstraction to leak. On x86. x86 and x86-64 usually do a good job of enforcing memory access order as if the instructions were executed sequentially. Other architectures, not so much. On PowerPC you had to put explicit memory barriers guaranteeing a certain access order with the 'eieio' instruction. ARM processors feature similar weak memory order, but the Apple M1 and later feature a special mode that guarantees strong x86-64 memory order, to make emulation for programs written for Intel Macs easier.