Vector pipelining is different from instruction pipelining. And the Itanic is a very different machine than a Cray-1. But in both cases the motivation is simila

Vector pipelining is different from instruction pipelining. And the Itanic is a very different machine than a Cray-1. But in both cases the motivation is similar: to avoid operations with a variable cycle time. The Cray has no variable time operations at all. All operations have fixed timing. This makes the implementation of vector pipelining much easier. The Itanic on the other hand relies on the compiler to instructions for optimal instruction pipelining. To do this the compiler needs to know the latency of the operations. For a x86 a reciprocal instruction makes less sense (except for vectors of course) since most x86 schedule instructions dynamically by hardware. It does make sense multiply with a constant instead of dividing, etc. But a reciprocal doesnt.