4 ms·

Fair point on the RISC-II having non-fixed instruction sizes. In any case, I think it's weird that we've experienced semantic drift to the point that architect

by ummonk 1y ago

Fair point on the RISC-II having non-fixed instruction sizes. In any case, I think it's weird that we've experienced semantic drift to the point that architectures with instruction sets that are too large and complex to be considered reduced get referred to as RISC simply because they're load-store architectures with lots of registers.

brucehoult 1y ago
Which do you have in mind? I don't think newer things labelled as "RISC" have significantly (if at all) exceeded original 1985 ARM for complexity of an individual instruction, or 1990 IBM RS/6000 for sheer number of instructions, so unless you have a newer example this "semantic drift" happened 35-40 years ago in the first 5-10 years after publication of the first RISC papers. Arm64 of course hits both axes. While I think having a small number of instructions (at least optionally) is desirable for a number of reasons I don't see that as defining RISC. RISC is, I think, about instructions being uniform enough to not complicate the execution pipeline. If you keep the instructions to reading two registers and writing a result to one register, preferably after 1 clock cycle, then I don't think there is any number of different operations available on those 2 operands that would make something be not RISC any more. Some people think it's ok to read 3 input registers -- again, Arm since 1985. And everyone in floating point, since `±A*B±C` is the fundamental and most common operation in floating point algorithms and IEEE 754-2008 mandates that the operation be done without intermediate rounding. There are some manufacturers who have apparently thought "RISC" is a good marketing thing and put the label on things that I don't consider to be RISC. For example Microchip claims 8 bit PIC is RISC. It certainly isn't -- it's a classic accumulator architecture (as are Intel 8051 and 8080 and MOS 6602) with Acc-Mem and Mem-Acc instructions. Calling memory "registers" doesn't change that On the other hand Atmel AVR is clearly RISC. Also TI market the MSP430 as RISC. It's a lovely little minimalist 16 bit ISA very similar to PDP-11 and, like PDP-11, all the 2-operand arithmetic operations can be done memory-to-memory which is a definite RISC no-no. Original M68000 - also PDP-11 like -- has a better claim to being RISC as (like 8086) it at least kept everything except MOV{B,W,L} down to reg-mem. But, no, PIC and MSP430 are not RISC despite their manufacturers saying they are.

by ummonk 1y ago

brucehoult 1y ago

Which do you have in mind? I don't think newer things labelled as "RISC" have significantly (if at all) exceeded original 1985 ARM for complexity of an individual instruction, or 1990 IBM RS/6000 for sheer number of instructions, so unless you have a newer example this "semantic drift" happened 35-40 years ago in the first 5-10 years after publication of the first RISC papers. Arm64 of course hits both axes. While I think having a small number of instructions (at least optionally) is desirable for a number of reasons I don't see that as defining RISC. RISC is, I think, about instructions being uniform enough to not complicate the execution pipeline. If you keep the instructions to reading two registers and writing a result to one register, preferably after 1 clock cycle, then I don't think there is any number of different operations available on those 2 operands that would make something be not RISC any more. Some people think it's ok to read 3 input registers -- again, Arm since 1985. And everyone in floating point, since `±A*B±C` is the fundamental and most common operation in floating point algorithms and IEEE 754-2008 mandates that the operation be done without intermediate rounding. There are some manufacturers who have apparently thought "RISC" is a good marketing thing and put the label on things that I don't consider to be RISC. For example Microchip claims 8 bit PIC is RISC. It certainly isn't -- it's a classic accumulator architecture (as are Intel 8051 and 8080 and MOS 6602) with Acc-Mem and Mem-Acc instructions. Calling memory "registers" doesn't change that On the other hand Atmel AVR is clearly RISC. Also TI market the MSP430 as RISC. It's a lovely little minimalist 16 bit ISA very similar to PDP-11 and, like PDP-11, all the 2-operand arithmetic operations can be done memory-to-memory which is a definite RISC no-no. Original M68000 - also PDP-11 like -- has a better claim to being RISC as (like 8086) it at least kept everything except MOV{B,W,L} down to reg-mem. But, no, PIC and MSP430 are not RISC despite their manufacturers saying they are.