4 ms·
> Look at a modern CPU die. See those frame pointer registers? That stack management hardware? That’s real estate. Silicon. Transistor budget. You don't. What
by summa_tech 1y ago
> Look at a modern CPU die. See those frame pointer registers? That stack management hardware? That’s real estate. Silicon. Transistor budget.
You don't. What you see is caches, lots of caches. Huge vector register files. Massive TLBs.
Get real - learn something about modern chips and stop fighting 1980s battles.
- burnt-resistor 1y agoThis. They're shouting at the sky from whatever squirrels are running around their brains without understanding anything about real CPUs. It's somewhere between a shitpost and AI slop. They offered no better alternative except to bitch about how "imperfect" things are that work. I'd like to see their FOSHW RTL design, test bench, and formal verification for a green field multicore, pipelined, superscalar, SIMD RISC design competitive to RISC-V RV64GC or Arm 64.
- astrobe_ 1y agoMaybe Mill' CPU [1] or GreenArray's CPU [2] ? The sad thing is that nobody is going to buy these chips aside from niche products. You won't see them run a desktop or a smartphone, because if a CPU doesn't have a C compiler or a Javascript JIT "out of the box" so to speak, it has no hope to enter mass market products. Even Java had no chance. Some older ARM CPUs used to support for "Java bytecode execution" [3] but it never saw adoption. Your comment makes me think that there is some truth in TFA's title: a trait of many mental illnesses is that the person is not aware they have it - the Stockholm syndrome is probably not a mental illness, though. See what you are doing: "gatekeep" alternatives that don't play by the rules of the dominant architectures ("pipelined, superscalar SIMD RISC design"). [1] https://millcomputing.com/ https://millcomputing.com/ [2] Website currently has a certificate problem. IIRC, GA144 is a 144 cores asynchronous CPU. The cores' ISA is based on the primitives of the Forth language: next to no registers, instruction manipulating data on a data stack instead, separate from the call/return stack. [3] https://en.wikipedia.org/wiki/Jazelle https://en.wikipedia.org/wiki/Jazelle
- estimator7292 1y agoJazelle shambled a lot further into the future than any of us want to admit. I think there are still a few ARM chips in production with java bytecode executuin still tacked on. Most of them only dropped it a few years ago.
- atq2119 1y agoYou forgot about branch predictors.
- shash 1y agoI mean, you can’t even see a single frame pointer register. The srams dominate everything else. Even the functional units are relatively cheap.