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Right, of course SPIR-V is a IR format for the drivers and not the final GPU machine code. I don't think WGSL is a bad language by any means, but I still find i
by Cloudef 1y ago
Right, of course SPIR-V is a IR format for the drivers and not the final GPU machine code. I don't think WGSL is a bad language by any means, but I still find it odd that the spec doesn't allow loading SPIR-V to cut out the extra transformation steps, and potential bugs or bad transformations in the WGSL implementation.
- greggman65 1y agoWhat makes you think there wouldn't be a translation step? The majority of the world is on DirectX and Metal, so even if it turn in SPIR-V there would be translation step.
- Cloudef 1y agoVulkan runs everywhere (apart from Apple ecosystem and browser), DirectX accepts SPIR-V nowadays.
- flohofwoe 1y agoAs far as I'm aware, any SPIRV isn't directly fed into the Vulkan backend, it's more like "WebGPU SPIRV => internal IR => validation => Vulkan SPIRV". Also I wouldn't rule out that some browser vendors will accept SPIRV as WebGPU shader input as a non-standard extension one day (disclaimer: talking out of my ass here since I'm not on any of the WebGPU implementation teams). The WebGPU API is prepared for accepting different types of shader inputs (that's how the native implementations accept SPIRV instead of WGSL). I bet that this would solve exactly zero problems though ;) > DirectX accepts SPIR-V nowadays That doesn't mean much since SPIRV has different incompatible flavours, e.g. you can't feed a GL SPIRV blob into Vulkan, or a Vulkan SPIRV blob into D3D (does D3D actually already accept SPIRV or is this still in the 'planning stage'?)
- torginus 1y agoSPIR-V is also a bad format for shaders (according to shader compiler devs): https://themaister.net/blog/2021/09/05/my-personal-hell-of-translating-dxil-to-spir-v-part-1/ https://themaister.net/blog/2021/09/05/my-personal-hell-of-t... The TLDR is SSA erases the structured control flow (like loops), which need to be recovered to support how branching is done on SIMD architectures (enabling/disabling lanes).