4 ms·
Not for VAX, see the recent thread on it [1]. [1] https://news.ycombinator.com/item?id=45378413 https://news.ycombinator.com/item?id=45378413
by rjsw 1y ago
Not for VAX, see the recent thread on it [1].
[1] https://news.ycombinator.com/item?id=45378413 https://news.ycombinator.com/item?id=45378413
- drob518 1y agoI’m not sure I get your point? Are you saying it is impossible to accelerate the VAX instruction set via the same technique used on x86? If so, you’ll have to explain why. Now, whether you’d want to or not is another question.
- p_l 1y agoYes, it's not possible to do it the same way, because what made x86 successful in their application is that x86 was remarkably RISC-y in actual behaviour compared to 68k or VAX. The main reason for that is that x86 code, outside of being register poor leading to lots of stack etc. use, decomposes most "ciscy" operations into LEA (inlined in pipeline) + memory access + actual operation. VAX (and to lesser extent, m68k and others) had multiple indirections just to get the operands right, way more than what is essentially single LEA instruction. The most complex VAX instructions could have been ignored as "this is super slow one and rarely used", but the burden of handling the indirections remain, including possible huge memory latency costs.
- clausecker 1y agoAlso, the VAX instruction encoding is a class of horror above that of x86.
- p_l 1y agofew classes above. Only ISA where I've seen a single instruction span two memory pages despite being page aligned
- brucehoult 1y agoTwo cache lines, sure, on earlier models, but not two VM pages!! Maximum instruction length is 56 bytes. Early models had 8 byte cache lines, later ones 64 bytes. VM page 512 bytes.
- p_l 1y agoI might be mistaken then, but I recall reading something about most extreme decode on VAX going into ~522 bytes. What I am more certain of was complaints about possibly ending with maaaany TLB lookups (and pagetable walks) for certain "business" optimized instructions.
- brucehoult 1y agoAbsolutely. Six operands [1], each of which can be in a different memory page AND have an indirection via another memory page AND both the indirection and the final operand could if you're unlucky be misaligned and straddle two memory pages ... ow. [1] MOVTC (Move Translated Character), MOVTUC (Move Translated Until Character), ADDP6 (Add Packed 6-operand)
- p_l 1y agoI think it was implied to me that every operand of ADDP6 could have been indirected, and all the resulting 3 ranges all could straddle pages.