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On a slightly different tangent, is anyone working on analog machine learning ASICs? Sub-threshold CMOS or something? I mean even at the research level? Usin
by floxy 1y ago
On a slightly different tangent, is anyone working on analog machine learning ASICs? Sub-threshold CMOS or something? I mean even at the research level? Using a handful of transistor for an analog multiplier. And get all of the crazy fascinating translinear stuff of Barrie Gilbert fame.
https://www.electronicdesign.com/technologies/analog/article/21807652/whats-all-this-subthreshold-stuff-anyhow https://www.electronicdesign.com/technologies/analog/article...
https://www.analog.com/en/resources/analog-dialogue/articles/considering-multipliers-part-1.html https://www.analog.com/en/resources/analog-dialogue/articles...
http://madvlsi.olin.edu/bminch/talks/090402_atact.pdf http://madvlsi.olin.edu/bminch/talks/090402_atact.pdf
- SmoothBrain123 1y ago[dead]
- nickpsecurity 1y agoA bunch of people. Just type these terms into DuckDuckGo: analog neural network hardware physical neural network hardware Put "this paper" after each one to get academic research. Try it with and without that phrase. Also, add "survey" to the next iteration. The papers that pop up will have the internal jargon the researchers use to describe their work. You can further search with it. The "this paper," "survey," and internal jargon in various combinations are how I find most CompSci things I share.
- xadhominemx 1y agoFor large models, the bottlenecks are memory bandwidth, network, and power consumption by the DAC/ADC arrays It’s never come even close to penciling out in practice. For small models there are people working on this implemented in flash memory eg Mythic.
- szundi 1y ago[dead]